[linux-dvb] Tuning problems with stv0297+tua6020 and QAM64
王 野
pifu21 at hotmail.com
Wed Nov 30 07:38:06 CET 2005
Hi all friends,
Sorry,my English is not perfect.
I had my DVB-C card(stv0297+tua6020) and tuning isn't work well.
I'm using dvb-kernel from cvs and porting it to my philips pnx1300 dsp.
I find when RF signal is weak, the equaliser partial convergence and full
convergence is ok,the tuner lock is ok and FEC work is ok,but when RF INPUT
signal is strong(maybe 70db), the equaliser convergence is ok,but tuner
lock is failed. Why is this?
I had try change some register of the stv0297,for example agc1,agc2,direct
gain,integral gain,but not solve this problem.
Please tell me ,how can I done in my stv0297 driver?
What register of the stv0297 is important about RF input signal strength ?
I need friend's help!
Thanks!
This is my stv0297 function:
int pllset (struct dvb_frontend_parameters *p)
{
UInt8 data[4];
UInt32 f_div;
int i,temp;
f_div=(p->frequency + 36000000 ) / 1000000;
f_div*=16;
data[0] = (f_div >> 8) & 0x7f;
data[1] = f_div & 0xff;
data[2] = 0x86;
if (p ->frequency < 45000000)
return 1;
else if (p ->frequency < 137000000)
data[3] = 0x01;
else if (p ->frequency < 403000000)
data[3] = 0x02;
else if (p ->frequency < 860000000)
data[3] = 0x04;
else
return 1;
stv0297_enable_plli2c( );
temp=iicwriteregs(0xc0,data[0],&data[1],3);
if (temp)
{
printf("iic writ front error\n");
}
else
printf(" front reg w %2x %2x %2x %2x
\n",data[0],data[1],data[2],data[3]);
for(i=0;i<100;i++)
{
stv0297_enable_plli2c( );
iicReadregs(0xc0,data,1);
if (data[0]&0x40)
break;
delay(1000);
}
printf("lock %d 0x%2x \n",i,data[0]);
return 0;
}
int stv0297_init ()
{
unsigned tuner;
int x=stv0297_readreg(0x82);
stv0297_writereg(0x85,0x80);
stv0297_writereg(0x86,0x88);
stv0297_writereg(0x87,0x13);
stv0297_writereg(0x88,0x00); //agc invert
stv0297_writereg(0x00,0x48 ); //0x48
stv0297_writereg(0x01,0x69); //0x69
stv0297_writereg(0x03,0x00); //0x00
stv0297_writereg(0x20,0x00);
stv0297_writereg(0x21,0x40);
stv0297_writereg(0x22,0x00);
stv0297_writereg(0x23,0x00);
stv0297_writereg(0x24,0x40);
stv0297_writereg(0x25,0x88); //0x88
stv0297_writereg(0x30,0xff); //agc2max 0xff
stv0297_writereg(0x31,0x00); //agc2min 0x00
stv0297_writereg(0x32,0xfd); //agc1max 0xfd
stv0297_writereg(0x33,0x00); //agc1min 0x0
stv0297_writereg(0x34,0x71); //ratio 0x71
stv0297_writereg(0x35,0x66); //agc2_thres 0x66
stv0297_writereg(0x36,0x80);
stv0297_writereg(0x37,0x60);
stv0297_writereg(0x38,0x00);
stv0297_writereg(0x40,0x1a); //0x1a
stv0297_writereg(0x41,0x00); //0xd0
stv0297_writereg(0x42,0x20); //0x21
stv0297_writereg(0x43,0x18); //0x18
stv0297_writereg(0x44,0x80); //0x80
stv0297_writereg(0x45,0x7f); //0x7f
stv0297_writereg(0x46,0x80); //0x80
stv0297_writereg(0x49,0x12); //0x12
stv0297_writereg(0x4a,0x5e); //0x5e
stv0297_writereg(0x4b,0xfa); //0xfa
stv0297_writereg(0x52,0x30);
stv0297_writereg(0x53,0x07);
stv0297_writereg(0x59,0x08); //0x08
stv0297_writereg(0x5a,0x1E); //0x1e
stv0297_writereg(0x5b,0x04); //0x04
stv0297_writereg(0x60,0x28); //xg
stv0297_writereg(0x61,0x2a); //0x39
stv0297_writereg(0x62,0x0); //0x50
stv0297_writereg(0x63,0x0);
stv0297_writereg(0x64,0x0);
stv0297_writereg(0x65,0x0);
stv0297_writereg(0x66,0x1c);
stv0297_writereg(0x67,0x25);
stv0297_writereg(0x68,0x00);
stv0297_writereg(0x69,0x00);
stv0297_writereg(0x6a,0x03); //0x02
stv0297_writereg(0x6b,0x00);
stv0297_writereg(0x70,0xff);
stv0297_writereg(0x71,0x04);
stv0297_writereg(0x72,0x00);
stv0297_writereg(0x73,0x00);
stv0297_writereg(0x74,0x00);
stv0297_writereg(0x89,0x00);
stv0297_writereg(0x90,0x02);
stv0297_writereg(0x91,0x02);
stv0297_writereg(0xa0,0x85); //0x85
stv0297_writereg(0xa1,0xc9); //0xc9
stv0297_writereg(0xa2,0xf6); //0xf6
stv0297_writereg(0xB0,0x91);
stv0297_writereg(0xB1,0x0b);
stv0297_writereg(0xc0,0x4b);
stv0297_writereg(0xc1,0x00);
stv0297_writereg(0xc2,0x00);
stv0297_writereg(0xde,0x00); //0x00
stv0297_writereg(0xdf,0x00);
stv0297_writereg(0xdf,0x01); //rs 0x00
return 0;
}
static int stv0297_set_frontend( struct dvb_frontend_parameters *p)
{
UInt8 value;
int WBAGC_Iref;
int initial_u;
int u_threshold;
long long_tmp;
int int_tmp;
int AGC2SD;
int TimeOut;
long CarrierOffset;
long SweepRate;
SweepRate=1000;
CarrierOffset=-10000;
pllset( p);
stv0297_writereg_mask(0x80,0x01,1);//BYTE Raddr,BYTE bmsk,BYTE data
stv0297_writereg_mask(0x80,0x01,0);//soft reset set bit 0 = 0
stv0297_writereg_mask(0x81,0x01,1);//reset DI set bit 0 = 1
stv0297_writereg_mask(0x81,0x01,0);
stv0297_init ();
stv0297_writereg_mask(0x25,0x80,0x80);
stv0297_writereg_mask(0x87,0x80,0x00);
WBAGC_Iref=stv0297_readreg(0x40);
stv0297_writereg_mask(0x43,0x10,0x00);
stv0297_writereg_mask(0x43,0x40,0x40);
stv0297_writereg_mask(0x43,0x08,0x00);
stv0297_writereg(0x41,0x00);
stv0297_writereg_mask(0x42,0x03,0x01);
stv0297_writereg_mask(0x36,0x60,0x00);
stv0297_writereg_mask(0x36,0x18,0x00);
stv0297_writereg_mask(0x71,0x80,0x80);
stv0297_writereg(0x72,0x00);
stv0297_writereg(0x73,0x00);
stv0297_writereg_mask(0x74,0x0F,0x00);
stv0297_writereg_mask(0x5A,0x20,0x20);
stv0297_writereg_mask(0x5B,0x02,0x02);
stv0297_writereg_mask(0x5B,0x02,0x00);
stv0297_writereg_mask(0x5B,0x01,0x00);
stv0297_writereg_mask(0x5A,0x40,0x00);
if (p->symbol_rate <3000000) // <3 Mbd
{
if (p->modulation<=QAM_64)
stv0297_writereg(0x61,0x49);
else
stv0297_writereg(0x61,0x4A);
}
else
{
if (p->modulation<=QAM_64)
stv0297_writereg(0x61,0x48);
else
stv0297_writereg(0x61,0x49);
}
stv0297_writereg(0x63,0x00);
stv0297_writereg(0x64,0x00);
stv0297_writereg(0x65,0x00);
stv0297_writereg(0x66,0x00);
stv0297_writereg(0x67,0x00);
stv0297_writereg(0x68,0x00);
stv0297_writereg_mask(0x69,0x0F,0x00);
stv0297_writereg_mask(0x6A,0x01,0x00);
// Equalizer values capture //
u_threshold = stv0297_readreg(0x00)&0x0f ;
initial_u = stv0297_readreg(0x01);
// Equalizer clear //
stv0297_writereg_mask(0x84,0x01,0x01);
stv0297_writereg_mask(0x84,0x01,0x00);
// Equalizer values reload //
stv0297_writereg_mask(0x00,0x0f,u_threshold);
stv0297_writereg_mask(0x01,0xf0,(initial_u & 0xf0));
stv0297_writereg_mask(0x01,0x0f,(initial_u & 0x0f));
stv0297_writereg_mask(0x82,0x08,0);
stv0297_writereg_mask(0x81,0x01,1); //reset DI
stv0297_writereg_mask(0x81,0x01,0);
stv0297_writereg_mask(0x90,0x80,0x80);
stv0297_writereg_mask(0x90,0x80,0x00);
stv0297_writereg_mask(0x85,0x20,0x00);
stv0297_writereg_mask(0x85,0x02,0x00);
stv0297_writereg_mask(0x90,0x03,0x02);
stv0297_writereg_mask(0x83,0x10,0x10);
stv0297_writereg_mask(0x83,0x10,0x00);
//set QAM //
stv0297_set_qam( p->modulation); //64 qam
//set SymbolRate //
stv0297_set_symbolrate (p->symbol_rate/1000); //6875000
//set SweepRate //
stv0297_set_sweeprate( SweepRate , p->symbol_rate/1000);
//set FrequencyOffset //
stv0297_set_carrieroffset( CarrierOffset);
// set inversion
stv0297_set_inversion( p->inversion);
//
stv0297_writereg_mask(0x88, 0x08,0x08);
stv0297_writereg_mask(0x5A, 0x20,0x00);
stv0297_writereg_mask(0x43, 0x10,0x10);
return 0;
}
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