[linux-dvb] Twinhan DVB Cab/CI (2031) problems

Raido raidoz at hot.ee
Tue Aug 15 22:14:22 CEST 2006


Ok, attached my dmesg from scan -v "myscanfile". scan didn't return 
anything, only >>> tuning status == 0x00. But  get this, strangely scan -c 
returns the channels that are on that frequency. Tried 2 frequencies. No 
dmesg from scan -c though. So basically the card tunes but the driver 
doesn't understand it? Using latest hg.
-------------- next part --------------
dst(0) dst_set_freq: set Frequency 386000000
dst(0) dst_set_frontend: Set Frequency=[386000000]
dst(0) dst_set_symbolrate: set symrate 6875000
dst(0) dst_set_symbolrate: DCT-CI
dst(0) dst_write_tuna: type_flags 0x1219 
dst(0) dst_comm_init: Initializing DST.
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0001], outhigh=[0000]
dst(0) rdc_reset_state: Resetting state machine
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0000]
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0002]
writing [ 09 00 05 e3 d0 00 1a db 40 0a ]
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0000], outhigh=[0000]
dst(0) read_dst: reply is 0xff
dst(0) dst_wait_dst_ready: dst wait ready after 2
dst(0) read_dst: reply is 0x9
 0x0 0x5 0xe3 0xd0 0x0 0x1a 0xdb 0x40 0xa
dst(0) dst_get_tuna: checksum failure? 
dst(0) dst_set_freq: set Frequency 386000000
dst(0) dst_set_frontend: Set Frequency=[386000000]
dst(0) dst_set_symbolrate: set symrate 6875000
dst(0) dst_set_symbolrate: DCT-CI
dst(0) dst_write_tuna: type_flags 0x1219 
dst(0) dst_comm_init: Initializing DST.
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0001], outhigh=[0000]
dst(0) rdc_reset_state: Resetting state machine
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0000]
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0002]
writing [ 09 00 05 e3 d0 00 1a db 40 0a ]
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0000], outhigh=[0000]
dst(0) read_dst: reply is 0xff
dst(0) dst_wait_dst_ready: dst wait ready after 2
dst(0) read_dst: reply is 0x9
 0x0 0x5 0xe3 0xd0 0x0 0x1a 0xdb 0x40 0xa
dst(0) dst_get_tuna: checksum failure? 
dst(0) dst_set_freq: set Frequency 386000000
dst(0) dst_set_frontend: Set Frequency=[386000000]
dst(0) dst_set_symbolrate: set symrate 6875000
dst(0) dst_set_symbolrate: DCT-CI
dst(0) dst_write_tuna: type_flags 0x1219 
dst(0) dst_comm_init: Initializing DST.
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0001], outhigh=[0000]
dst(0) rdc_reset_state: Resetting state machine
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0000]
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0002]
writing [ 09 00 05 e3 d0 00 1a db 40 0a ]
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0000], outhigh=[0000]
dst(0) read_dst: reply is 0xff
dst(0) dst_wait_dst_ready: dst wait ready after 2
dst(0) read_dst: reply is 0x9
 0x0 0x5 0xe3 0xd0 0x0 0x1a 0xdb 0x40 0xa
dst(0) dst_get_tuna: checksum failure? 
dst(0) dst_set_freq: set Frequency 386000000
dst(0) dst_set_frontend: Set Frequency=[386000000]
dst(0) dst_set_symbolrate: set symrate 6875000
dst(0) dst_set_symbolrate: DCT-CI
dst(0) dst_write_tuna: type_flags 0x1219 
dst(0) dst_comm_init: Initializing DST.
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0001], outhigh=[0000]
dst(0) rdc_reset_state: Resetting state machine
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0000]
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0002]
writing [ 09 00 05 e3 d0 00 1a db 40 0a ]
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0000], outhigh=[0000]
dst(0) read_dst: reply is 0xff
dst(0) dst_wait_dst_ready: dst wait ready after 2
dst(0) read_dst: reply is 0x9
 0x0 0x5 0xe3 0xd0 0x0 0x1a 0xdb 0x40 0xa
dst(0) dst_get_tuna: checksum failure? 
dst(0) dst_set_freq: set Frequency 386000000
dst(0) dst_set_frontend: Set Frequency=[386000000]
dst(0) dst_set_symbolrate: set symrate 6875000
dst(0) dst_set_symbolrate: DCT-CI
dst(0) dst_write_tuna: type_flags 0x1219 
dst(0) dst_comm_init: Initializing DST.
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0001], outhigh=[0000]
dst(0) rdc_reset_state: Resetting state machine
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0000]
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0002]
writing [ 09 00 05 e3 d0 00 1a db 40 0a ]
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0000], outhigh=[0000]
dst(0) read_dst: reply is 0xff
dst(0) dst_wait_dst_ready: dst wait ready after 2
dst(0) read_dst: reply is 0x9
 0x0 0x5 0xe3 0xd0 0x0 0x1a 0xdb 0x40 0xa
dst(0) dst_get_tuna: checksum failure? 
dst(0) dst_set_freq: set Frequency 386000000
dst(0) dst_set_frontend: Set Frequency=[386000000]
dst(0) dst_set_symbolrate: set symrate 6875000
dst(0) dst_set_symbolrate: DCT-CI
dst(0) dst_write_tuna: type_flags 0x1219 
dst(0) dst_comm_init: Initializing DST.
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0001], outhigh=[0000]
dst(0) rdc_reset_state: Resetting state machine
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0000]
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0002]
writing [ 09 00 05 e3 d0 00 1a db 40 0a ]
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0000], outhigh=[0000]
dst(0) read_dst: reply is 0xff
dst(0) dst_wait_dst_ready: dst wait ready after 2
dst(0) read_dst: reply is 0x9
 0x0 0x5 0xe3 0xd0 0x0 0x1a 0xdb 0x40 0xa
dst(0) dst_get_tuna: checksum failure? 
dst(0) dst_set_freq: set Frequency 386000000
dst(0) dst_set_frontend: Set Frequency=[386000000]
dst(0) dst_set_symbolrate: set symrate 6875000
dst(0) dst_set_symbolrate: DCT-CI
dst(0) dst_write_tuna: type_flags 0x1219 
dst(0) dst_comm_init: Initializing DST.
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0001], outhigh=[0000]
dst(0) rdc_reset_state: Resetting state machine
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0000]
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0002]
writing [ 09 00 05 e3 d0 00 1a db 40 0a ]
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0000], outhigh=[0000]
dst(0) read_dst: reply is 0xff
dst(0) dst_wait_dst_ready: dst wait ready after 2
dst(0) read_dst: reply is 0x9
 0x0 0x5 0xe3 0xd0 0x0 0x1a 0xdb 0x40 0xa
dst(0) dst_get_tuna: checksum failure? 
dst(0) dst_set_freq: set Frequency 386000000
dst(0) dst_set_frontend: Set Frequency=[386000000]
dst(0) dst_set_symbolrate: set symrate 6875000
dst(0) dst_set_symbolrate: DCT-CI
dst(0) dst_write_tuna: type_flags 0x1219 
dst(0) dst_comm_init: Initializing DST.
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0001], outhigh=[0000]
dst(0) rdc_reset_state: Resetting state machine
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0000]
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0002]
writing [ 09 00 05 e3 d0 00 1a db 40 0a ]
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0000], outhigh=[0000]
dst(0) read_dst: reply is 0xff
dst(0) dst_wait_dst_ready: dst wait ready after 2
dst(0) read_dst: reply is 0x9
 0x0 0x5 0xe3 0xd0 0x0 0x1a 0xdb 0x40 0xa
dst(0) dst_get_tuna: checksum failure? 
dst(0) dst_set_freq: set Frequency 386000000
dst(0) dst_set_frontend: Set Frequency=[386000000]
dst(0) dst_set_symbolrate: set symrate 6875000
dst(0) dst_set_symbolrate: DCT-CI
dst(0) dst_write_tuna: type_flags 0x1219 
dst(0) dst_comm_init: Initializing DST.
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0001], outhigh=[0000]
dst(0) rdc_reset_state: Resetting state machine
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0000]
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0002]
writing [ 09 00 05 e3 d0 00 1a db 40 0a ]
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0000], outhigh=[0000]
dst(0) read_dst: reply is 0xff
dst(0) dst_wait_dst_ready: dst wait ready after 2
dst(0) read_dst: reply is 0x9
 0x0 0x5 0xe3 0xd0 0x0 0x1a 0xdb 0x40 0xa
dst(0) dst_get_tuna: checksum failure? 
dst(0) dst_set_freq: set Frequency 386000000
dst(0) dst_set_frontend: Set Frequency=[386000000]
dst(0) dst_set_symbolrate: set symrate 6875000
dst(0) dst_set_symbolrate: DCT-CI
dst(0) dst_write_tuna: type_flags 0x1219 
dst(0) dst_comm_init: Initializing DST.
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0001], outhigh=[0000]
dst(0) rdc_reset_state: Resetting state machine
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0000]
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0002]
writing [ 09 00 05 e3 d0 00 1a db 40 0a ]
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0000], outhigh=[0000]
dst(0) read_dst: reply is 0xff
dst(0) dst_wait_dst_ready: dst wait ready after 2
dst(0) read_dst: reply is 0x9
 0x0 0x5 0xe3 0xd0 0x0 0x1a 0xdb 0x40 0xa
dst(0) dst_get_tuna: checksum failure? 
dst(0) dst_set_freq: set Frequency 386000000
dst(0) dst_set_frontend: Set Frequency=[386000000]
dst(0) dst_set_symbolrate: set symrate 6875000
dst(0) dst_set_symbolrate: DCT-CI
dst(0) dst_write_tuna: type_flags 0x1219 
dst(0) dst_comm_init: Initializing DST.
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0001], outhigh=[0000]
dst(0) rdc_reset_state: Resetting state machine
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0000]
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0002]
writing [ 09 00 05 e3 d0 00 1a db 40 0a ]
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0000], outhigh=[0000]
dst(0) read_dst: reply is 0xff
dst(0) dst_wait_dst_ready: dst wait ready after 2
dst(0) read_dst: reply is 0x9
 0x0 0x5 0xe3 0xd0 0x0 0x1a 0xdb 0x40 0xa
dst(0) dst_get_tuna: checksum failure? 
dst(0) dst_set_freq: set Frequency 386000000
dst(0) dst_set_frontend: Set Frequency=[386000000]
dst(0) dst_set_symbolrate: set symrate 6875000
dst(0) dst_set_symbolrate: DCT-CI
dst(0) dst_write_tuna: type_flags 0x1219 
dst(0) dst_comm_init: Initializing DST.
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0001], outhigh=[0000]
dst(0) rdc_reset_state: Resetting state machine
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0000]
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0002]
writing [ 09 00 05 e3 d0 00 1a db 40 0a ]
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0000], outhigh=[0000]
dst(0) read_dst: reply is 0xff
dst(0) dst_wait_dst_ready: dst wait ready after 2
dst(0) read_dst: reply is 0x9
 0x0 0x5 0xe3 0xd0 0x0 0x1a 0xdb 0x40 0xa
dst(0) dst_get_tuna: checksum failure? 
dst(0) dst_set_freq: set Frequency 386000000
dst(0) dst_set_frontend: Set Frequency=[386000000]
dst(0) dst_set_symbolrate: set symrate 6875000
dst(0) dst_set_symbolrate: DCT-CI
dst(0) dst_write_tuna: type_flags 0x1219 
dst(0) dst_comm_init: Initializing DST.
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0001], outhigh=[0000]
dst(0) rdc_reset_state: Resetting state machine
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0000]
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0002]
writing [ 09 00 05 e3 d0 00 1a db 40 0a ]
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0000], outhigh=[0000]
dst(0) read_dst: reply is 0xff
dst(0) dst_wait_dst_ready: dst wait ready after 2
dst(0) read_dst: reply is 0x9
 0x0 0x5 0xe3 0xd0 0x0 0x1a 0xdb 0x40 0xa
dst(0) dst_get_tuna: checksum failure? 
dst(0) dst_set_freq: set Frequency 386000000
dst(0) dst_set_frontend: Set Frequency=[386000000]
dst(0) dst_set_symbolrate: set symrate 6875000
dst(0) dst_set_symbolrate: DCT-CI
dst(0) dst_write_tuna: type_flags 0x1219 
dst(0) dst_comm_init: Initializing DST.
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0001], outhigh=[0000]
dst(0) rdc_reset_state: Resetting state machine
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0000]
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0002]
writing [ 09 00 05 e3 d0 00 1a db 40 0a ]
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0000], outhigh=[0000]
dst(0) read_dst: reply is 0xff
dst(0) dst_wait_dst_ready: dst wait ready after 2
dst(0) read_dst: reply is 0x9
 0x0 0x5 0xe3 0xd0 0x0 0x1a 0xdb 0x40 0xa
dst(0) dst_get_tuna: checksum failure? 
dst(0) dst_set_freq: set Frequency 386000000
dst(0) dst_set_frontend: Set Frequency=[386000000]
dst(0) dst_set_symbolrate: set symrate 6875000
dst(0) dst_set_symbolrate: DCT-CI
dst(0) dst_write_tuna: type_flags 0x1219 
dst(0) dst_comm_init: Initializing DST.
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0001], outhigh=[0000]
dst(0) rdc_reset_state: Resetting state machine
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0000]
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0002]
writing [ 09 00 05 e3 d0 00 1a db 40 0a ]
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0000], outhigh=[0000]
dst(0) read_dst: reply is 0xff
dst(0) dst_wait_dst_ready: dst wait ready after 2
dst(0) read_dst: reply is 0x9
 0x0 0x5 0xe3 0xd0 0x0 0x1a 0xdb 0x40 0xa
dst(0) dst_get_tuna: checksum failure? 
dst(0) dst_set_freq: set Frequency 386000000
dst(0) dst_set_frontend: Set Frequency=[386000000]
dst(0) dst_set_symbolrate: set symrate 6875000
dst(0) dst_set_symbolrate: DCT-CI
dst(0) dst_write_tuna: type_flags 0x1219 
dst(0) dst_comm_init: Initializing DST.
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0001], outhigh=[0000]
dst(0) rdc_reset_state: Resetting state machine
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0000]
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0002]
writing [ 09 00 05 e3 d0 00 1a db 40 0a ]
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0000], outhigh=[0000]
dst(0) read_dst: reply is 0xff
dst(0) dst_wait_dst_ready: dst wait ready after 2
dst(0) read_dst: reply is 0x9
 0x0 0x5 0xe3 0xd0 0x0 0x1a 0xdb 0x40 0xa
dst(0) dst_get_tuna: checksum failure? 
dst(0) dst_set_freq: set Frequency 386000000
dst(0) dst_set_frontend: Set Frequency=[386000000]
dst(0) dst_set_symbolrate: set symrate 6875000
dst(0) dst_set_symbolrate: DCT-CI
dst(0) dst_write_tuna: type_flags 0x1219 
dst(0) dst_comm_init: Initializing DST.
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0001], outhigh=[0000]
dst(0) rdc_reset_state: Resetting state machine
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0000]
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0002]
writing [ 09 00 05 e3 d0 00 1a db 40 0a ]
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0000], outhigh=[0000]
dst(0) read_dst: reply is 0xff
dst(0) dst_wait_dst_ready: dst wait ready after 2
dst(0) read_dst: reply is 0x9
 0x0 0x5 0xe3 0xd0 0x0 0x1a 0xdb 0x40 0xa
dst(0) dst_get_tuna: checksum failure? 
dst(0) dst_set_freq: set Frequency 386000000
dst(0) dst_set_frontend: Set Frequency=[386000000]
dst(0) dst_set_symbolrate: set symrate 6875000
dst(0) dst_set_symbolrate: DCT-CI
dst(0) dst_write_tuna: type_flags 0x1219 
dst(0) dst_comm_init: Initializing DST.
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0001], outhigh=[0000]
dst(0) rdc_reset_state: Resetting state machine
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0000]
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0002]
writing [ 09 00 05 e3 d0 00 1a db 40 0a ]
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0000], outhigh=[0000]
dst(0) read_dst: reply is 0xff
dst(0) dst_wait_dst_ready: dst wait ready after 2
dst(0) read_dst: reply is 0x9
 0x0 0x5 0xe3 0xd0 0x0 0x1a 0xdb 0x40 0xa
dst(0) dst_get_tuna: checksum failure? 
dst(0) dst_set_freq: set Frequency 386000000
dst(0) dst_set_frontend: Set Frequency=[386000000]
dst(0) dst_set_symbolrate: set symrate 6875000
dst(0) dst_set_symbolrate: DCT-CI
dst(0) dst_write_tuna: type_flags 0x1219 
dst(0) dst_comm_init: Initializing DST.
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0001], outhigh=[0000]
dst(0) rdc_reset_state: Resetting state machine
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0000]
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0002]
writing [ 09 00 05 e3 d0 00 1a db 40 0a ]
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0000], outhigh=[0000]
dst(0) read_dst: reply is 0xff
dst(0) dst_wait_dst_ready: dst wait ready after 2
dst(0) read_dst: reply is 0x9
 0x0 0x5 0xe3 0xd0 0x0 0x1a 0xdb 0x40 0xa
dst(0) dst_get_tuna: checksum failure? 
dst(0) dst_set_freq: set Frequency 386000000
dst(0) dst_set_frontend: Set Frequency=[386000000]
dst(0) dst_set_symbolrate: set symrate 6875000
dst(0) dst_set_symbolrate: DCT-CI
dst(0) dst_write_tuna: type_flags 0x1219 
dst(0) dst_comm_init: Initializing DST.
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0001], outhigh=[0000]
dst(0) rdc_reset_state: Resetting state machine
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0000]
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0002]
writing [ 09 00 05 e3 d0 00 1a db 40 0a ]
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0000], outhigh=[0000]
dst(0) read_dst: reply is 0xff
dst(0) dst_wait_dst_ready: dst wait ready after 2
dst(0) read_dst: reply is 0x9
 0x0 0x5 0xe3 0xd0 0x0 0x1a 0xdb 0x40 0xa
dst(0) dst_get_tuna: checksum failure? 
dst(0) dst_set_freq: set Frequency 386000000
dst(0) dst_set_frontend: Set Frequency=[386000000]
dst(0) dst_set_symbolrate: set symrate 6875000
dst(0) dst_set_symbolrate: DCT-CI
dst(0) dst_write_tuna: type_flags 0x1219 
dst(0) dst_comm_init: Initializing DST.
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0001], outhigh=[0000]
dst(0) rdc_reset_state: Resetting state machine
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0000]
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0002]
writing [ 09 00 05 e3 d0 00 1a db 40 0a ]
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0000], outhigh=[0000]
dst(0) read_dst: reply is 0xff
dst(0) dst_wait_dst_ready: dst wait ready after 2
dst(0) read_dst: reply is 0x9
 0x0 0x5 0xe3 0xd0 0x0 0x1a 0xdb 0x40 0xa
dst(0) dst_get_tuna: checksum failure? 
dst(0) dst_set_freq: set Frequency 386000000
dst(0) dst_set_frontend: Set Frequency=[386000000]
dst(0) dst_set_symbolrate: set symrate 6875000
dst(0) dst_set_symbolrate: DCT-CI
dst(0) dst_write_tuna: type_flags 0x1219 
dst(0) dst_comm_init: Initializing DST.
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0001], outhigh=[0000]
dst(0) rdc_reset_state: Resetting state machine
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0000]
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0002]
writing [ 09 00 05 e3 d0 00 1a db 40 0a ]
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0000], outhigh=[0000]
dst(0) read_dst: reply is 0xff
dst(0) dst_wait_dst_ready: dst wait ready after 2
dst(0) read_dst: reply is 0x9
 0x0 0x5 0xe3 0xd0 0x0 0x1a 0xdb 0x40 0xa
dst(0) dst_get_tuna: checksum failure? 
dst(0) dst_set_freq: set Frequency 386000000
dst(0) dst_set_frontend: Set Frequency=[386000000]
dst(0) dst_set_symbolrate: set symrate 6875000
dst(0) dst_set_symbolrate: DCT-CI
dst(0) dst_write_tuna: type_flags 0x1219 
dst(0) dst_comm_init: Initializing DST.
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0001], outhigh=[0000]
dst(0) rdc_reset_state: Resetting state machine
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0000]
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0002]
writing [ 09 00 05 e3 d0 00 1a db 40 0a ]
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0000], outhigh=[0000]
dst(0) read_dst: reply is 0xff
dst(0) dst_wait_dst_ready: dst wait ready after 2
dst(0) read_dst: reply is 0x9
 0x0 0x5 0xe3 0xd0 0x0 0x1a 0xdb 0x40 0xa
dst(0) dst_get_tuna: checksum failure? 
dst(0) dst_set_freq: set Frequency 386000000
dst(0) dst_set_frontend: Set Frequency=[386000000]
dst(0) dst_set_symbolrate: set symrate 6875000
dst(0) dst_set_symbolrate: DCT-CI
dst(0) dst_write_tuna: type_flags 0x1219 
dst(0) dst_comm_init: Initializing DST.
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0001], outhigh=[0000]
dst(0) rdc_reset_state: Resetting state machine
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0000]
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0002]
writing [ 09 00 05 e3 d0 00 1a db 40 0a ]
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0000], outhigh=[0000]
dst(0) read_dst: reply is 0xff
dst(0) dst_wait_dst_ready: dst wait ready after 2
dst(0) read_dst: reply is 0x9
 0x0 0x5 0xe3 0xd0 0x0 0x1a 0xdb 0x40 0xa
dst(0) dst_get_tuna: checksum failure? 
dst(0) dst_set_freq: set Frequency 386000000
dst(0) dst_set_frontend: Set Frequency=[386000000]
dst(0) dst_set_symbolrate: set symrate 6875000
dst(0) dst_set_symbolrate: DCT-CI
dst(0) dst_write_tuna: type_flags 0x1219 
dst(0) dst_comm_init: Initializing DST.
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0001], outhigh=[0000]
dst(0) rdc_reset_state: Resetting state machine
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0000]
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0002]
writing [ 09 00 05 e3 d0 00 1a db 40 0a ]
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0000], outhigh=[0000]
dst(0) read_dst: reply is 0xff
dst(0) dst_wait_dst_ready: dst wait ready after 42
dst(0) read_dst: reply is 0x9
 0x0 0x5 0xe3 0xd0 0x0 0x1a 0xdb 0x40 0xa
dst(0) dst_get_tuna: checksum failure? 
dst(0) dst_set_freq: set Frequency 386000000
dst(0) dst_set_frontend: Set Frequency=[386000000]
dst(0) dst_set_symbolrate: set symrate 6875000
dst(0) dst_set_symbolrate: DCT-CI
dst(0) dst_write_tuna: type_flags 0x1219 
dst(0) dst_comm_init: Initializing DST.
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0001], outhigh=[0000]
dst(0) rdc_reset_state: Resetting state machine
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0000]
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0002]
writing [ 09 00 05 e3 d0 00 1a db 40 0a ]
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0000], outhigh=[0000]
dst(0) read_dst: reply is 0xff
dst(0) dst_wait_dst_ready: dst wait ready after 42
dst(0) read_dst: reply is 0x9
 0x0 0x5 0xe3 0xd0 0x0 0x1a 0xdb 0x40 0xa
dst(0) dst_get_tuna: checksum failure? 
dst(0) dst_set_freq: set Frequency 386000000
dst(0) dst_set_frontend: Set Frequency=[386000000]
dst(0) dst_set_symbolrate: set symrate 6875000
dst(0) dst_set_symbolrate: DCT-CI
dst(0) dst_write_tuna: type_flags 0x1219 
dst(0) dst_comm_init: Initializing DST.
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0001], outhigh=[0000]
dst(0) rdc_reset_state: Resetting state machine
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0000]
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0002]
writing [ 09 00 05 e3 d0 00 1a db 40 0a ]
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0000], outhigh=[0000]
dst(0) read_dst: reply is 0xff
dst(0) dst_wait_dst_ready: dst wait ready after 42
dst(0) read_dst: reply is 0x9
 0x0 0x5 0xe3 0xd0 0x0 0x1a 0xdb 0x40 0xa
dst(0) dst_get_tuna: checksum failure? 
dst(0) dst_set_freq: set Frequency 386000000
dst(0) dst_set_frontend: Set Frequency=[386000000]
dst(0) dst_set_symbolrate: set symrate 6875000
dst(0) dst_set_symbolrate: DCT-CI
dst(0) dst_write_tuna: type_flags 0x1219 
dst(0) dst_comm_init: Initializing DST.
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0001], outhigh=[0000]
dst(0) rdc_reset_state: Resetting state machine
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0000]
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0002]
writing [ 09 00 05 e3 d0 00 1a db 40 0a ]
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0000], outhigh=[0000]
dst(0) read_dst: reply is 0xff
dst(0) dst_wait_dst_ready: dst wait ready after 42
dst(0) read_dst: reply is 0x9
 0x0 0x5 0xe3 0xd0 0x0 0x1a 0xdb 0x40 0xa
dst(0) dst_get_tuna: checksum failure? 
dst(0) dst_set_freq: set Frequency 386000000
dst(0) dst_set_frontend: Set Frequency=[386000000]
dst(0) dst_set_symbolrate: set symrate 6875000
dst(0) dst_set_symbolrate: DCT-CI
dst(0) dst_write_tuna: type_flags 0x1219 
dst(0) dst_comm_init: Initializing DST.
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0001], outhigh=[0000]
dst(0) rdc_reset_state: Resetting state machine
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0000]
dst(0) dst_gpio_outb: mask=[0002], enbb=[0002], outhigh=[0002]
writing [ 09 00 05 e3 d0 00 1a db 40 0a ]
dst(0) dst_gpio_outb: mask=[ffffffff], enbb=[0000], outhigh=[0000]
dst(0) read_dst: reply is 0xff
dst(0) dst_wait_dst_ready: dst wait ready after 42
dst(0) read_dst: reply is 0x9
 0x0 0x5 0xe3 0xd0 0x0 0x1a 0xdb 0x40 0xa
dst(0) dst_get_tuna: checksum failure? 


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