[linux-dvb] Re: [PATCH] i2c_gate_ctrl QT1010, ZL10353 (and GL861 AU6610)

[Antti Palosaari]

Christopher Pascoe wrote:
>> ZL10353:
>> - implement i2c_gate_ctrl
> 
> This looks to be OK, but I haven't had an opportunity to test it yet.
> 
>> - change one reset_attach register to same as main v4l-dvb tree
> 
> Hmm, what do you mean?

oops, this was due to fix made for gl861 by comabug... I didn't find any 
difference between 0x03 or 0x0b so it is safer to leave original value 
from your driver.
http://linuxtv.org/hg/~mkrufky/megasky.old?cmd=changeset;node=2417cff7cf81;style=gitweb

> 
>> - leave registers 0x65 and 0x66 to chipset default one... This change 
>> could *break* some other devices using ZL10353 module! Testing needed! 
>> This change is needed to get Megasky GL861 and Sigmatek AU6610 working.
> 
> NAK.  0x65/0x66 seems to be the "nominal rate" register.  Its setting will 
> depend on the OFDM bandwidth of the channel being tuned and the crystal on 
> board.  I think the currently working boards all have a 20.48MHz crystal 
> and tune only 7MHz bandwidth OFDM.  Are you 20.48MHz crystal and 8MHz 
> bandwidth OFDM?  If so, we should add the appropriate infrastructure here 
> to select the right values based on what the user is trying to tune.

I did correct(?) nominal rate 65/66 calculation last night based on 
mt312 driver. It takes some time to find correct xtal value :) because 
of I don't understand why it is needed 22528 kHz instead of 20480 kHz. 
 From the pics I can see there is 20480 kHz xtal in hw and mt312 driver 
also defaults to it. Xtal is seen here: 
http://otit.fi/~crope/v4l-dvb/Sigmatek_DVB-110/2006-11-11_Sigmatek_DVB-110/IMG_2028.JPG 
. Does anyone have idea why the value used in code differs from value 
actual xtal??? Should I default zl10353 driver xtal (in code value) to 
20480 or 22528 ? Probably I will default it to 22528 and users can 
override it if needed. I will send nominal rate patch later tonight.

Here is the values which demod changes between different bandwidths:

BW 6:
I2C demod W 64 30
I2C demod W 65 4d
I2C demod W 66 ec
I2C demod W cc dd
I2C demod W 56 31
I2C demod W 5c 9c

BW7:
I2C demod W 64 35
I2C demod W 65 5a
I2C demod W 66 e9
I2C demod W cc 73
I2C demod W 56 2b
I2C demod W 5c 86

BW8:
I2C demod W 64 36
I2C demod W 65 67
I2C demod W 66 e5
I2C demod W cc 73
I2C demod W 56 2b
I2C demod W 5c 75

As you can see, we must still find out and implement registers 64, cc, 
56 and 5c. It will take some time (week or two) but I will continue to 
fix those. It helps a lot that we have already a good implementation of 
the MT312.

/antti
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