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ported to kernel 2.6 (by Anssi Hannula)

#ifndef __SAA711X_H__
#define __SAA711X_H__


#define PH7113_CHIP_VERSION                   0x00
// (READ ONLY) 
// ID07 ID06 ID05 ID04 - - - -

#define PH7113_INCREMENT_DELAY                0x01
// (1) (1) (1) (1) IDEL3 IDEL2 IDELL1 IDEL0

#define PH7113_ANALOG_INPUT_CONTR_1           0x02
// FUSE1 FUSE0 GUDL1 GUDL0 MODE3 MODE2 MODE1 MODE0

#define PH7113_ANALOG_INPUT_CONTR_2           0x03
// (1) HLNRS VBSL WPOFF HOLDG GAFIX GAI28 GAI18

#define PH7113_ANALOG_INPUT_CONTR_3           0x04
// GAI17 GAI16 GAI15 GAI14 GAI13 GAI12 GAI11 GAI10

#define PH7113_ANALOG_INPUT_CONTR_4           0x05
// GAI27 GAI26 GAI25 GAI24 GAI23 GAI22 GAI21 GAI20

#define PH7113_HORIZONTAL_SYNC_START          0x06
// HSB7 HSB6 HSB5 HSB4 HSB3 HSB2 HSB1 HSB0

#define PH7113_HORIZONTAL_SYNC_STOP           0x07
// HSS7 HSS6 HSS5 HSS4 HSS3 HSS2 HSS1 HSS0

#define PH7113_SYNC_CONTROL                   0x08
// AUFD FSEL FOET HTC1 HTC0 HPLL VNOI1 VNOI0

#define PH7113_LUMINANCE_CONTROL              0x09
// BYPS PREF BPSS1 BPSS0 VBLB UPTCV APER1 APER0

#define PH7113_LUMINANCE_BRIGHTNESS           0x0A
// BRIG7 BRIG6 BRIG5 BRIG4 BRIG3 BRIG2 BRIG1 BRIG0

#define PH7113_LUMINANCE_CONTRAST             0x0B
// CONT7 CONT6 CONT5 CONT4 CONT3 CONT2 CONT1 CONT0

#define PH7113_CHROMA_SATURATION              0x0C
// SATN7 SATN6 SATN5 SATN4 SATN3 SATN2 SATN1 SATN0

#define PH7113_CHROMA_HUE_CONTROL             0x0D
// HUEC7 HUEC6 HUEC5 HUEC4 HUEC3 HUEC2 HUEC1 HUEC0

#define PH7113_CHROMA_CONTROL                 0x0E
// CDTO CSTD2 CSTD1 CSTD0 DCCF FCTC CHBW1 CHBW0

#define PH7113_CHROMA_GAIN_CONTROL            0x0F
// ACGC CGAIN6 CGAIN5 CGAIN4 CGAIN3 CGAIN2 CGAIN1 CGAIN0

#define PH7113_FORMAT_DELAY_CONTROL           0x10
// OFTS1 OFTS0 HDEL1 HDEL0 VRLN YDEL2 YDEL1 YDEL0

#define PH7113_OUTPUT_CONTROL_1               0x11
// GPSW1 CM99 GPSW0 HLSEL OEYC OERT VIPB COLO

#define PH7113_OUTPUT_CONTROL_2               0x12
// RTSE13 RTSE12 RTSE11 RTSE10 RTSE03 RTSE02 RTSE01 RTSE00

#define PH7113_OUTPUT_CONTROL_3               0x13
// ADLSB (1) (1) OLDSB FIDP (1) AOSL1 AOSL0

// RESERVED 14 
// (1) (1) (1) (1) (1) (1) (1) (1)

#define PH7113_V_GATE1_START                  0x15
// VSTA7 VSTA6 VSTA5 VSTA4 VSTA3 VSTA2 VSTA1 VSTA0

#define PH7113_V_GATE1_STOP                   0x16
// VSTO7 VSTO6 VSTO5 VSTO4 VSTO3 VSTO2 VSTO1 VSTO0

#define PH7113_V_GATE1_MSB                    0x17
// (1) (1) (1) (1) (1) (1) VSTO8 VSTA8

// RESERVED 18-1E 
// (1) (1) (1) (1) (1) (1) (1) (1)

#define PH7113_STATUS_BYTE_0                  0x1F
// (READ ONLY, OLDSB=0) 
// INTL HLVLN FIDT GLIMT GLIMB WIPA COPRO RDCAP
#define DETECT_COLOR_SIGNAL               0x01
#define HOR_FREQUENCY_LOCKED              0x40

#define PH7113_STATUS_BYTE_1                  0x1F
 // (READ ONLY, OLDSB=1) 
// INTL HLCK FIDT GLIMT GLIMB WIPA SLTCA CODE

// 20H TO 3FH RESERVED 20 -3F 
// (1) (1) (1) (1) (1) (1) (1) (1)

#define PH7113_AC1                            0x40
// FISET HAM_N FCE HUNT_N (1) CLKSEL1 CLKSEL0 (1)

#define PH7113_LCR2                           0x41
// LCR02_7 LCR02_6 LCR02_5 LCR02_4 LCR02_3 LCR02_2 LCR02_1 LCR02_0

#define PH7113_LCR3                           0x42
#define PH7113_LCR4                           0x43
#define PH7113_LCR5                           0x44
#define PH7113_LCR6                           0x45
#define PH7113_LCR7                           0x46
#define PH7113_LCR8                           0x47
#define PH7113_LCR9                           0x48
#define PH7113_LCR10                          0x49
#define PH7113_LCR11                          0x4A
#define PH7113_LCR12                          0x4B
#define PH7113_LCR13                          0x4C
#define PH7113_LCR14                          0x4D
#define PH7113_LCR15                          0x4E
#define PH7113_LCR16                          0x4F
#define PH7113_LCR17                          0x50
#define PH7113_LCR18                          0x51
#define PH7113_LCR19                          0x52
#define PH7113_LCR20                          0x53
#define PH7113_LCR21                          0x54
#define PH7113_LCR22                          0x55
#define PH7113_LCR23                          0x56
// LCRN_7 LCRN_6 LCRN_5 LCRN_4 LCRN_3 LCRN_2 LCRN_1 LCRN_0

#define PH7113_LCR24                          0x57
// LCR24_7 LCR24_6 LCR24_5 LCR24_4 LCR24_3 LCR24_2 LCR24_1 LCR24_0

#define PH7113_FC                             0x58
// FC7 FC6 FC5 FC4 FC3 FC2 FC1 FC0

#define PH7113_HOFF                           0x59
// HOFF7 HOFF6 HOFF5 HOFF4 HOFF3 HOFF2 HOFF1 HOFF0

#define PH7113_VOFF                           0x5A
// VOFF7 VOFF6 VOFF5 VOFF4 VOFF3 VOFF2 VOFF1 VOFF0

#define PH7113_HVOFF                          0x5B
// FOFF (1) (1) VOFF8 (1) HOFF10 HOFF9 HOFF8

//( FOR TESTABILITY ) 5C (1) (1) (1) (1) (1) (1) (1) (1)

//RESERVED 5D 
// (1) (1) (1) (1) (1) (1) (1) (1)

#define PH7113_SLICED_DATA_ID_CODE            0x5E
// (1) (1) SDID5 SDID4 SDID3 SDID2 SDID1 SDID0

// RESERVED 5F 
// (1) (1) (1) (1) (1) (1) (1) (1)

#define PH7113_DR                             0x60
// (READ ONLY) 
// FC8V FC7V VPSV PPV CCV - - -

#define PH7113_LN1                            0x61
// (READ ONLY) 
// - - F21_N LN8 LN7 LN6 LN5 LN4

#define PH7113_LN2                            0x62
// (READ ONLY) 
// LN3 LN2 LN1 LN0 DT3 DT2 DT1 DT0

//RESERVED FOR FUTURE EXTENSIONS 63 TO FF
// (1) (1) (1) (1) (1) (1) (1) (1)

#define PH7113_MAX_PARAMS                     PH7113_LN2

// 1. All unused control bits must be programmed with logic 0 to ensure compatibility to future enhancements

#endif				// __SAA711X_H__