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| pinchartl | hverkuil: ping | [13:48] |
| hverkuil | pinchartl: pong | [14:01] |
| pinchartl | quick question for you
regarding the VSP driver the hardware has a scaler in newer SoCs the line buffers for the scaler have been reduced in such a way that scaling images wider than 256 pixels isn't possible the CPU needs to partition the image in slices, and run a processing pass for each slice the hardware has a command buffer mechanism that can be used to prepare processing of all slices with register values for each run and then start processing, with an interrupt generated after the last run only the question is whether slicing should be implemented in the kernel driver or if we should tell userspace to deal with it in which case an interrupt would be generated after each slice, with a QBUF/DQBUF cycle I would push it back to userspace to have less work, if it wasn't for the fact that - older generations don't have that limitation, so it would change the userspace API for new SoCs - the hardware has the ability to pipeline slices, but that requires computing register values for all slices in one go, requiring slicing in the driver any opinion ? | [14:02] |
| hverkuil | I think you answered your own question! If at all possible you want to hide this awful design in the kernel driver.
Do HW and SW engineers ever talk to one another? Apparently not... | [14:07] |
| pinchartl | maybe, but the SW engineers certainly don't talk to the upstream team in time for the hardware design to be fixed :-)
thanks for your opinion, I'll do that in kernelspace then | [14:10] |
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