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[13:48] <pinchartl> hverkuil: ping
[14:01] <hverkuil> pinchartl: pong
[14:02] <pinchartl> quick question for you
[14:02] <pinchartl> regarding the VSP driver
[14:02] <pinchartl> the hardware has a scaler
[14:02] <pinchartl> in newer SoCs the line buffers for the scaler have been reduced
[14:03] <pinchartl> in such a way that scaling images wider than 256 pixels isn't possible
[14:03] <pinchartl> the CPU needs to partition the image in slices, and run a processing pass for each slice
[14:04] <pinchartl> the hardware has a command buffer mechanism that can be used to prepare processing of all slices
[14:04] <pinchartl> with register values for each run
[14:04] <pinchartl> and then start processing, with an interrupt generated after the last run only
[14:04] <pinchartl> the question is whether slicing should be implemented in the kernel driver
[14:05] <pinchartl> or if we should tell userspace to deal with it
[14:05] <pinchartl> in which case an interrupt would be generated after each slice, with a QBUF/DQBUF cycle
[14:06] <pinchartl> I would push it back to userspace to have less work, if it wasn't for the fact that
[14:06] <pinchartl> - older generations don't have that limitation, so it would change the userspace API for new SoCs
[14:07] <pinchartl> - the hardware has the ability to pipeline slices, but that requires computing register values for all slices in one go, requiring slicing in the driver
[14:07] <pinchartl> any opinion ?
[14:07] <hverkuil> I think you answered your own question! If at all possible you want to hide this awful design in the kernel driver.
[14:08] <hverkuil> Do HW and SW engineers ever talk to one another? Apparently not...
[14:10] <pinchartl> maybe, but the SW engineers certainly don't talk to the upstream team in time for the hardware design to be fixed :-)
[14:10] <pinchartl> thanks for your opinion, I'll do that in kernelspace then
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