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uajain: Is there a case where V4L2_CTRL_FLAG_MODIFY_LAYOUT is not meant for V4L2_CID_VFLIP?
<br> I see many drivers setting the flag with vflip and I am wondering it's better to set the flag for vflip in v4l2-ctrls-defs.c
jmondi: <u>uajain</u>: some drivers adjust the crop rectangle by +- 1 pixel to maintain the bayer pattern
<br> iirc some sensor do that automatically (maybe I'm remembering wrong, as it seems unlikely)
<br> so it's not guaranteed that v/hflip == V4L2_CTRL_FLAG_MODIFY_LAYOUT
uajain: Oh, I se
<br> s/se/see
hverkuil: And video receivers typically do not need the flag either.
kbingham: uajain, Hopefully - you won't need it on IMX283 as the arbitrary window cropping/positioning already prevents 'odd' line positions, so hopefully they handle the offset when flipping so that only the correct bayer order still comes out.
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tomba: If I have a 60-bit bus, on which I get two 30-bit RGB pixels, 10-bits per component, would that be MEDIA_BUS_FMT_RGB101010_0_5X60 ?
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sailus: <u>tomba</u>: I was just reading a sensor spec and they had pictures of an American school bus there so I thought immediately your question was about an autobus.
<br> pinchartl educated me that in French they have solved this by introducing a new word for a bus in context of computers, it is "bitoduc" (compare with "aqueduc").
<br> <u>tomba</u>: Why 5X60?
tomba: 0_5X60
sailus: Seldom there have been cases where a single bus cycle has transferred multiple groups of pixels.
tomba: I feel I'm too often dealing with seldoms
sailus: Ah.
<br> Shouldn't the ending be 0_5_1X60 instead?
<br> No, wait. I think you're right.
<br> Yes. My ack on that.
tomba: https://docs.xilinx.com/r/en-US/pg103-v-tpg/Video-Data
<br> unfortunately the YUV 4:2:0 pics are broken on that page, so we don't know what they're like
sailus: <u>tomba</u>: When you're writing a patch for this, could you add the 0,5 case to the documentation as well? It's there for YUV formats but not for RGB.
<br> The same patch should do fine.
tomba: ah, indeed
<br> <u>sailus</u>: and still on the topic of seldoms, if you looked at the web page, you perhaps noticed that the format is not RGB, but RBG...
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tomba: Hmm, no, the bus is actually 64 bits... Should the media bus fmt only mention the used bits? Is the 8-bits-per-component format on that same bus MEDIA_BUS_FMT_RGB888_0_5X48?
sailus: <u>tomba</u>: This is presumably an internal bus, so you wouldn't be connecting other devices there?
<br> In that case I'd think it doesn't really matter much.
<br> <u>pinchartl</u>: Any thoughts? ^
tomba: Well... With FPGAs... You can't know what the users will be doing =)
sailus: It could be a 65-bit bus, I guess?
tomba: I think the IPs require a bus width that's divisible by 8
<br> it would be nice to avoid creating a lot of mbus formats, though
sailus: This probably matters more when the bus transports a pixel (group) over multiple clock cycles.
<br> I think I'd avoid putting the padding there.
<br> <u>hverkuil</u>: ^
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pinchartl: <u>tomba</u>: I would just ignore the 4 extra bits
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pinchartl: has something changed in the kernel doc build system recently, or is it just my system that can't compile the kernel doc anymore ? :-(
<br> The sphinxcontrib.devhelp extension used by this project needs at least Sphinx v5.0; it therefore cannot be built with this version.
<br> (using the python venv from the kernel)
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