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| tfiga | pinchartl: I think it could be useful for some kind of "dummy" buffers, e.g. when a device needs to be continuously fed with buffers, but one is only getting some DMA-bufs from an upper layer for frames which the upper layer cares about
would be good to hear about your use cases, though | [03:11] |
| pinchartl | it's related to dummy buffers too
where we get dmabuf buffers from the application but we need to allocate a dummy buffer at runtime we'll probably end up allocating it before starting the camera though | [03:19] |
| tfiga | I see, thanks
one thing that we had to deal with back in time was a capture interface which would need a restart if it runs out of buffers and in that case it may not be great to rely on the user space continuously providing buffers so we ended up having a buffer allocated internally by the driver that was used repeatedly when no user provided buffer was avaialble (that was actually rkisp1) | [03:30] |
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| jmassot | kbingham: Finally the video mux is perhaps not the best for the targeted project, the plan is to have two pipeline running concurrently at 25 FPS. Does someone know a real aggregator device like we have with the GMSL and FPD Link device? | [09:30] |
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| kbingham | jmassot, I thought the device you pointed to was a multiplexor ? I.e. it can only choose one stream of data ?
If your end device is different then I would expect some custom driver perhaps... or is it just more of an intelligent 'switch/router' for the data lanes? - I know we'd like to look at replacing video-mux with something new that can support internal routing and extra features.... but we just need a reason to work on it ;-) | [09:34] |
| jmassot | kbingham: it's basically a switch so you should set the gpio exactly at the right instant to have concurrent streaming, e.g not in a middle of a CSI frame, I'm also thinking that if both sensor are using different CSI settings e.g the link frequency then the CSI receiver might get confused | [09:37] |
| kbingham | jmassot, Err... so you're giong to dynamically change the gpio between frames to get multiple transmitters connected to a receiver ....
that sounds ... complicated ;-) | [09:38] |
| jmassot | kbingham: yeah that's not what we need :D | [09:38] |
| kbingham | phew!
That's absolutely something that should be handled in hardware with buffering and timing all in hardware ;D | [09:39] |
| jmassot | kbingham: Yes that's what the FPD link/ GMSL devices are doing | [09:39] |
| kbingham | yes, but they are not a video mux.
We've started here because you showed a device that looks very much like a video mux - but now the target device is ... not a video mux ... Your opening question here was "Does someone know a real aggregator device like GMSL and FPD Link" ... well - yes - those... ? So perhaps there is a deeper meaning to your question that I've missed ? | [09:40] |
| jmassot | kbingham: Yes GMSL and FPD Link device are a bit too much complicated if there are no cable length/ signal quality issues right | [09:43] |
| kbingham | jmassot, Are you looking for a device to buy ... or trying to build software for something that exists...
Maybe I'm looking at your questions from the wrong angle - I thought you were trying to support something you already have, but now I'm thinking your earlier in the phase looking for hardware selection... | [09:44] |
| jmassot | kbingham: a device to buy yes, the design is still open | [09:45] |
| kbingham | Aha right - sorry - I was in the wrong place ;-D | [09:45] |
| jmassot | kbingham: there was a first proposal for the MIPI switcher but it doesn't match the use cases | [09:46] |
| kbingham | So - what are the requirements, if GMSL and FPD-Link don't fit ? | [09:46] |
| jmassot | kbingham: GMSL and FPD link fit they are perhaps too much complicated if the sensor are located very near to the SoC | [09:47] |
| kbingham | So you need multiple parallel inputs - but you're restricted to a single CSI2 receiver? | [09:47] |
| jmassot | kbingham: Yes, this is for an AM62x SoC with only one the CSI receiver | [09:48] |
| kbingham | There will be a lot of complexity there for buffering, and timing, or aligning each stream to have a different VC...
I don't know of an existing off the shelf part for this - but I know of some of our customers who do similar things with an FPGA in the middle. | [09:49] |
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| jmassot | kbingham: Got it thanks for the information :) | [09:51] |
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