just in case attaching my "lspci -vvnx". Thank you much. doug.
#lspci -vvnx
00:00.0 Class 0600: 1106:3112
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort+ >SERR- <PERR-
Latency: 8
Region 0: Memory at d0000000 (32-bit, prefetchable) [size=64M]
Capabilities: [a0] AGP version 2.0
Status: RQ=7 SBA+ 64bit- FW- Rate=x1,x2,x4
Command: RQ=0 SBA- AGP- 64bit- FW- Rate=<none>
Capabilities: [c0] Power Management version 2
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 06 11 12 31 06 00 10 22 00 00 00 06 00 08 00 00
10: 08 00 00 d0 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00
00:01.0 Class 0604: 1106:b112
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort+ >SERR- <PERR+
Latency: 0
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
Memory behind bridge: d4000000-d6ffffff
BridgeCtl: Parity- SERR- NoISA+ VGA+ MAbort- >Reset- FastB2B-
Capabilities: [80] Power Management version 2
Flags: PMEClk- DSI- D1+ D2- AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 06 11 12 b1 07 00 30 a2 00 00 04 06 00 00 01 00
10: 00 00 00 00 00 00 00 00 00 01 01 00 f0 00 00 00
20: 00 d4 f0 d6 f0 ff 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 0c 00
00:07.0 Class 0601: 1106:0686 (rev 40)
Subsystem: 1106:0000
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping+ SERR- FastB2B-
Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Latency: 0
Capabilities: [c0] Power Management version 2
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 06 11 86 06 87 00 10 02 40 00 01 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 00 00
30: 00 00 00 00 c0 00 00 00 00 00 00 00 00 00 00 00
00:07.1 Class 0101: 1106:0571 (rev 06) (prog-if 8a [Master SecP PriP])
Subsystem: 1106:0571
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Latency: 32
Region 4: I/O ports at e000 [size=16]
Capabilities: [c0] Power Management version 2
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 06 11 71 05 07 00 90 02 06 8a 01 01 00 20 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 01 e0 00 00 00 00 00 00 00 00 00 00 06 11 71 05
30: 00 00 00 00 c0 00 00 00 00 00 00 00 ff 00 00 00
00:07.2 Class 0c03: 1106:3038 (rev 1a)
Subsystem: 0925:1234
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Latency: 32, cache line size 08
Interrupt: pin D routed to IRQ 3
Region 4: I/O ports at e400 [size=32]
Capabilities: [80] Power Management version 2
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 06 11 38 30 07 00 10 02 1a 00 03 0c 08 20 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 01 e4 00 00 00 00 00 00 00 00 00 00 25 09 34 12
30: 00 00 00 00 80 00 00 00 00 00 00 00 03 04 00 00
00:07.3 Class 0c03: 1106:3038 (rev 1a)
Subsystem: 0925:1234
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Latency: 32, cache line size 08
Interrupt: pin D routed to IRQ 3
Region 4: I/O ports at e800 [size=32]
Capabilities: [80] Power Management version 2
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 06 11 38 30 07 00 10 02 1a 00 03 0c 08 20 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 01 e8 00 00 00 00 00 00 00 00 00 00 25 09 34 12
30: 00 00 00 00 80 00 00 00 00 00 00 00 03 04 00 00
00:07.4 Class 0680: 1106:3057 (rev 40)
Subsystem: 1106:3057
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Interrupt: pin ? routed to IRQ 9
Capabilities: [68] Power Management version 2
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 06 11 57 30 00 00 90 02 40 00 80 06 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 57 30
30: 00 00 00 00 68 00 00 00 00 00 00 00 00 00 00 00
00:08.0 Class 0200: 1317:0985 (rev 11)
Subsystem: 1317:0574
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Latency: 32 (63750ns min, 63750ns max), cache line size 08
Interrupt: pin A routed to IRQ 11
Region 0: I/O ports at ec00 [size=256]
Region 1: Memory at d8000000 (32-bit, non-prefetchable)
[size=1K]
Expansion ROM at <unassigned> [disabled] [size=128K]
Capabilities: [c0] Power Management version 2
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=100mA
PME(D0+,D1+,D2+,D3hot+,D3cold+)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 17 13 85 09 07 00 90 02 11 00 00 02 08 20 00 00
10: 01 ec 00 00 00 00 00 d8 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 17 13 74 05
30: 00 00 00 00 c0 00 00 00 00 00 00 00 0b 01 ff ff
00:0a.0 Class 0480: 1131:7146 (rev 01)
Subsystem: 1131:4f56
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Latency: 32 (3750ns min, 9500ns max)
Interrupt: pin A routed to IRQ 10
Region 0: Memory at d8001000 (32-bit, non-prefetchable)
[size=512]
00: 31 11 46 71 06 00 80 02 01 00 80 04 00 20 00 00
10: 00 10 00 d8 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 31 11 56 4f
30: 00 00 00 00 00 00 00 00 00 00 00 00 0a 01 0f 26
01:00.0 Class 0300: 1023:8500
Subsystem: 1023:8500
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Latency: 32
Interrupt: pin A routed to IRQ 11
Region 0: Memory at d5800000 (32-bit, non-prefetchable)
[size=8M]
Region 1: Memory at d6000000 (32-bit, non-prefetchable)
[size=128K]
Region 2: Memory at d5000000 (32-bit, non-prefetchable)
[size=8M]
Expansion ROM at <unassigned> [disabled] [size=64K]
Capabilities: [80] AGP version 1.0
Status: RQ=32 SBA+ 64bit- FW- Rate=x1,x2,x4
Command: RQ=0 SBA- AGP- 64bit- FW- Rate=<none>
Capabilities: [90] Power Management version 1
Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 23 10 00 85 07 00 b0 02 00 00 00 03 00 20 00 00
10: 00 00 80 d5 00 00 00 d6 00 00 00 d5 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 23 10 00 85
30: 00 00 00 00 80 00 00 00 00 00 00 00 0b 01 00 00
-----Original Message-----
From: linux-dvb-bounce@linuxtv.org
[mailto:linux-dvb-bounce@linuxtv.org] On Behalf Of Holger Waechtler
Sent: Saturday, August 16, 2003 5:43 PM
To: doug
Cc: linux-dvb@linuxtv.org
Subject: [linux-dvb] Re: difference between su-1278/sh and su-1278/sh2
doug wrote:
sorry, that was 1.0.0, typo there,
anyways, what i am looking are pll_set_tv_freq(), stv0299_init().
my understanding is that for example,
- sta5059 i2c data structure is like below
start-device address(C2 for sta5059)-data(1byte)-continue
data(1byte)-data(1byte)-stop
- but, tua6100 i2c structure's a little different from 5059,
start-device address(C0 for tua6100)-subaddress(register of
6100-00H
to 03H for write, 80H for read) data(1byte)-data(1byte)-stop
everybody who writes values onto 6100pll must put device address
followed by register(00H~03H), but 5059 code doesn't seem
like that.
where the difference comes from? old i2c spec or 7146
controller? so
interesting! guessing i have to change 3 parts of the code
to control
PLL.
The tua6100 is not programmed using a 4- or 5-byte-string like most
other PLL/Synthesizers but instead it is register based and has 3
registers you have to program. Unfortunally the writes to these
registers have to meet some timing requirements, play with
the delays if
you get i2c errors.
besides, the biggest problem is have no idea what tuner
values(charge
pump current, synthesizer N-counter, R-counter and many
more) i have
to generate to make SU-1278SH/2(stv0299)+TUA 6100PLL work,
any data or
suggestions from somebody who specializes in tuner are
really required
for me to finish my job. many thanks, Doug.
Look into the datasheet for the exact meaning of the fields, but I
suppose the settings in the driver should work for the /SH2
too if you
ensure that this code path is taken. Maybe one or two bits
might have to
get set differently, don't know.
Do you have a reference driver, maybe a windows driver or
some reference
software from Philips you can use for comparision?
Holger
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