that is THE CLASSICAL MISTAKE ;-) .. A0-A11 are 12 lines, not 11 :-)
so we have here 24 bit and that is 16M
and i think we get another bit from the 16bit data bus, because
we are always reading LSB=0 and LSB=1 together
which are then 25 bit and 32M .. what a coincidence with the docu ;-)
there are ENOUGH adresslines solderd to the chip
No, see above.
yes ;-)
again:
the scs2 is allready routed to the osd ram chip ... i hope the
Don't think so.
why do you think that is not true? klaus told me that there are
two ram chips, every one with 2MB and he want to upgrade one
of them (the OSD one) to 4mb ... the lower bank has only
2 mb, and so the upper bank IS IN USE .. and if it is in use
it is using SCS2 to enable the chip .. this is totaly clear for me!
on page 63 :