[linux-dvb] networked digital tuner project
nuclearcat at nuclearcat.com
Sat Jun 11 14:32:23 CEST 2005
Âû ïèñàëè 11 èþíÿ 2005 ã., 3:28:30:
> Hi Wolfgang,
> Thanks for your input. Comments inline.
>> My idea would be to use an (embedded) processor for
>> all the control and network stuff, and have an FPGA
>> the TS handling (and demux). Like this you could
>> have a
>> DVB card that is not only usable for such a server
>> also for a "stand-alone" PC.
> My idea was at least initially to implement a very
> minimalist solution, keeping things as simple as
> possible. A single FPGA would implement a minimal
> Ethernet MAC, FIFOs to buffer data from the
> tuners/demods, an i2c master, and a small state
> machine to handle control packets. In this case, no
> CPU would be used in the device. All control of the
> tuners and parsing of the data would be done by the
> client PCs.
> If the data is multicast/UDP, then the state machines
> wouldn't even need to ARP, and of course wouldn't need
> to implement a TCP stack.
Take a look to Pent at Office. It is using pSOSystem OS. Powered by ARM processor, but it is networking solution.
Funny part - it is resolving gateway MAC by ARP only at boot time,
maybe it is even standalone application. So if gateway turned off
when Pent at Office booting - it will not work good later (will send
packets to mac 00:00:00:00:00:00.
There is not too much ways, IMHO, but easiest will be just
RF block + bt878-like chip + ARM cpu + Network chip(LAN91C111?)
Issue is, maybe if you want to save bandwidth, and use less powerful CPU,
good to use FlexCop, which have embedded PID filtering.
>> Advantage: you could maybe integrate some more fun
>> like packet time stamping (MPEG
>> accurate (synchronised) PCM/AC-3 output without
>> PCR synchronisation on board, section
>> control, etc. Of course this would then be more
>> for the stand-alone PC, but this is what I am really
>> missing from all the "solutions" available right
> The timestamping part would be easy. Reading the PCR
> values from the packets wouldn't be too hard in an
> FPGA, although it might not be much of an advantage if
> the card just sends MPEG-TS over ethernet. The tuners
> I was considering output a byte-parallel MPEG TS data
> stream. The time delay from demodulation to ethernet
> transmission would be very short.
>> Do you have FPGA experience? Are there other people
>> already working on such a thing? Anybody already
>> a video decoder in an FPGA, to have a new
>> board like this? ;-)
> I've done several FPGA designs in the past, and have
> some bits of VHDL code which can be leveraged for this
> design. A full video decoder is beyond my scope of
> experience, though.
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