Panasonic MN88472

MN88472

The MN88472 is a DVB-T/DVB-T2/DVB-C demodulator chip manufactured by Panasonic.

I2C Adressing

The chips has 3 I2C addresses, one for each demodulator bank:

8 bit (7 bit)
0x38  (0x1c) - DVB-T2 (T2)
0x30  (0x18) - DVB-T  (T1)
0x34  (0x1a) - DVB-C  (C1)

Demod Initialization

• Write init reg values for all 3 register banks (T2 T1 and C1) {bank,reg,value}

{T2,0x00,0x66},{T2,0x01,0x00},{T2,0x02,0x01},{T2,0x03,0x03},
{T2,0x04,0x00},{T2,0x05,0x00},{T2,0x06,0x00},{T2,0x07,0x00},
{T2,0x08,0x00},{T2,0x09,0x00},{T2,0x0a,0x00},{T2,0x0b,0x00},
{T2,0x0c,0x00},{T2,0x0d,0x00},{T2,0x0e,0x00},{T2,0x0f,0x00},
{T2,0x10,0x3e},{T2,0x11,0x70},{T2,0x12,0x64},{T2,0x13,0x8f},
{T2,0x14,0x80},{T2,0x15,0x00},{T2,0x16,0x08},{T2,0x17,0xee},
{T2,0x18,0x08},{T2,0x19,0xee},{T2,0x1a,0x43},{T2,0x1b,0x00},
{T2,0x1c,0x74},{T2,0x1d,0xe4},{T2,0x1e,0x26},{T2,0x1f,0x4f},
{T2,0x20,0x72},{T2,0x21,0x22},{T2,0x22,0x22},{T2,0x23,0x01},
{T2,0x24,0x00},{T2,0x25,0x12},{T2,0x26,0x00},{T2,0x27,0x00},
{T2,0x28,0x80},{T2,0x29,0x0c},{T2,0x2a,0xf4},{T2,0x2b,0x03},
{T2,0x2c,0x00},{T2,0x2d,0x20},{T2,0x2e,0x88},{T2,0x2f,0x00},
{T2,0x30,0x80},{T2,0x31,0x80},{T2,0x32,0x00},{T2,0x33,0x00},
{T2,0x34,0x00},{T2,0x35,0x00},{T2,0x36,0x00},{T2,0x37,0x00},
{T2,0x38,0xca},{T2,0x39,0x03},{T2,0x3a,0x02},{T2,0x3b,0x55},
{T2,0x3c,0xd7},{T2,0x3d,0x00},{T2,0x3e,0x00},{T2,0x3f,0x22},
{T2,0x40,0x00},{T2,0x41,0x38},{T2,0x42,0x22},{T2,0x43,0x00},
{T2,0x44,0x38},{T2,0x45,0xd3},{T2,0x46,0x10},{T2,0x47,0xb5},
{T2,0x48,0xa1},{T2,0x49,0x00},{T2,0x4a,0xd3},{T2,0x4b,0x07},
{T2,0x4c,0x64},{T2,0x4d,0x0d},{T2,0x4e,0x00},{T2,0x4f,0x05},
{T2,0x50,0x00},{T2,0x51,0x55},{T2,0x52,0x20},{T2,0x53,0x00},
{T2,0x54,0x24},{T2,0x55,0x64},{T2,0x56,0x44},{T2,0x57,0x33},
{T2,0x58,0x1f},{T2,0x59,0x00},{T2,0x5a,0x5a},{T2,0x5b,0x03},
{T2,0x5c,0xc0},{T2,0x5d,0x00},{T2,0x5e,0x00},{T2,0x5f,0x03},
{T2,0x60,0x00},{T2,0x61,0x00},{T2,0x62,0x11},{T2,0x63,0x40},
{T2,0x64,0x84},{T2,0x65,0x04},{T2,0x66,0x0c},{T2,0x67,0x00},
{T2,0x68,0x08},{T2,0x69,0x00},{T2,0x6a,0x00},{T2,0x6b,0x12},
{T2,0x6c,0x21},{T2,0x6d,0x10},{T2,0x6e,0x01},{T2,0x6f,0x00},
{T2,0x70,0x00},{T2,0x71,0x00},{T2,0x72,0xe8},{T2,0x73,0x48},
{T2,0x74,0x40},{T2,0x75,0x00},{T2,0x76,0x1d},{T2,0x77,0x19},
{T2,0x78,0x1d},{T2,0x79,0x19},{T2,0x7a,0x66},{T2,0x7b,0x8c},
{T2,0x7c,0x9f},{T2,0x7d,0x08},{T2,0x7e,0x00},{T2,0x7f,0x00},
{T2,0x80,0x00},{T2,0x81,0x00},{T2,0x83,0x00},{T2,0x84,0x00},
{T2,0x85,0x00},{T2,0x86,0x00},{T2,0x87,0x00},{T2,0x88,0x00},
{T2,0x89,0x00},{T2,0x8a,0x20},{T2,0x8b,0x49},{T2,0x8c,0x00},
{T2,0xc4,0x00},{T2,0xc5,0x00},{T2,0xc6,0x00},{T2,0xc7,0x87},
{T2,0xc8,0x40},{T2,0xc9,0x30},{T2,0xca,0x06},{T2,0xcb,0x02},
{T2,0xcc,0x00},{T2,0xcd,0x3b},{T2,0xce,0x00},{T2,0xcf,0x00},
{T2,0xd0,0x00},{T2,0xd1,0x00},{T2,0xd2,0x00},{T2,0xd3,0x40},
{T2,0xd4,0x00},{T2,0xd5,0xf0},{T2,0xd6,0x02},{T2,0xd7,0x02},
{T2,0xd8,0x01},{T2,0xd9,0x00},{T2,0xda,0x00},{T2,0xdb,0x00},
{T2,0xdc,0x00},{T2,0xdd,0x00},{T2,0xde,0x00},{T2,0xdf,0x00},
{T2,0xe0,0x00},{T2,0xe1,0x00},{T2,0xe2,0x00},{T2,0xe3,0x00},
{T2,0xe4,0x00},{T2,0xe5,0x00},{T2,0xe6,0x00},{T2,0xe7,0x00},
{T2,0xe9,0x00},{T2,0xea,0x00},{T2,0xeb,0x00},{T2,0xec,0xd3},
{T2,0xed,0x31},{T2,0xee,0x00},{T2,0xef,0x00},{T2,0xf0,0x00},
{T2,0xf1,0x00},{T2,0xf2,0x00},{T2,0xf3,0x00},{T2,0xf4,0x00},
{T2,0xf5,0x00},{T2,0xf6,0x00},{T2,0xf8,0x9f},{T2,0xf9,0xd4},
{T2,0xfa,0x00},{T2,0xfb,0x03},{T2,0xfc,0x00},{T2,0xfd,0x00},
{T2,0xfe,0x00},{T2,0xff,0x02},{T1,0x00,0xba},{T1,0x01,0x13},
{T1,0x02,0x80},{T1,0x03,0xba},{T1,0x04,0x91},{T1,0x05,0x40},
{T1,0x06,0xe7},{T1,0x07,0x26},{T1,0x08,0xff},{T1,0x09,0x1b},
{T1,0x0a,0x09},{T1,0x0b,0x08},{T1,0x0c,0x04},{T1,0x0d,0x2d},
{T1,0x0e,0x09},{T1,0x0f,0x00},{T1,0x10,0x10},{T1,0x11,0x1f},
{T1,0x12,0x08},{T1,0x13,0x00},{T1,0x14,0x00},{T1,0x15,0x03},
{T1,0x16,0x00},{T1,0x17,0x00},{T1,0x18,0x00},{T1,0x19,0xb0},
{T1,0x1a,0x00},{T1,0x1b,0x00},{T1,0x1c,0x00},{T1,0x1d,0xe0},
{T1,0x1e,0x6c},{T1,0x1f,0x33},{T1,0x20,0x4a},{T1,0x21,0x03},
{T1,0x22,0x00},{T1,0x23,0x01},{T1,0x24,0x05},{T1,0x25,0x96},
{T1,0x26,0x43},{T1,0x27,0x00},{T1,0x28,0x01},{T1,0x29,0x15},
{T1,0x2a,0xa2},{T1,0x2b,0xc3},{T1,0x2c,0xf5},{T1,0x2d,0x22},
{T1,0x2e,0x87},{T1,0x2f,0xd3},{T1,0x30,0x00},{T1,0x31,0x55},
{T1,0x32,0x33},{T1,0x33,0x61},{T1,0x34,0x22},{T1,0x35,0x01},
{T1,0x36,0x02},{T1,0x37,0x40},{T1,0x38,0x40},{T1,0x39,0x46},
{T1,0x3a,0x25},{T1,0x3b,0x04},{T1,0x3c,0x00},{T1,0x3d,0x04},
{T1,0x3e,0x00},{T1,0x3f,0x00},{T1,0x40,0x3b},{T1,0x41,0x20},
{T1,0x42,0x00},{T1,0x43,0x3f},{T1,0x44,0x1f},{T1,0x45,0x05},
{T1,0x46,0x00},{T1,0x47,0x00},{T1,0x48,0x05},{T1,0x49,0xf0},
{T1,0x4a,0x00},{T1,0x4b,0x00},{T1,0x4c,0x1f},{T1,0x4d,0x0f},
{T1,0x4e,0x39},{T1,0x4f,0x03},{T1,0x50,0xf8},{T1,0x51,0xf4},
{T1,0x52,0x08},{T1,0x53,0xf8},{T1,0x54,0xea},{T1,0x55,0xf0},
{T1,0x56,0x04},{T1,0x57,0x20},{T1,0x58,0x12},{T1,0x59,0x12},
{T1,0x5a,0x02},{T1,0x5b,0x20},{T1,0x5c,0x1a},{T1,0x5d,0x08},
{T1,0x5e,0xad},{T1,0x5f,0x33},{T1,0x60,0x95},{T1,0x61,0x8f},
{T1,0x62,0x80},{T1,0x63,0x00},{T1,0x64,0x76},{T1,0x65,0x54},
{T1,0x66,0x87},{T1,0x67,0x65},{T1,0x68,0x66},{T1,0x69,0x54},
{T1,0x6a,0x4a},{T1,0x6b,0x86},{T1,0x6c,0x13},{T1,0x6d,0x31},
{T1,0x6e,0x2d},{T1,0x6f,0x07},{T1,0x70,0x00},{T1,0x71,0x40},
{T1,0x72,0x00},{T1,0x73,0x00},{T1,0x74,0x00},{T1,0x75,0x10},
{T1,0x76,0x0c},{T1,0x77,0x0c},{T1,0x78,0x59},{T1,0x79,0x00},
{T1,0x7a,0x00},{T1,0x7b,0x00},{T1,0x7c,0x00},{T1,0x7d,0x05},
{T1,0x88,0x1e},{T1,0x89,0x49},{T1,0x8a,0x31},{T1,0x8b,0x1a},
{T1,0x8c,0x2c},{T1,0x8d,0x3f},{T1,0x8e,0x7f},{T1,0x8f,0x07},
{T1,0xa5,0x00},{T1,0xa6,0x00},{T1,0xa9,0x00},{T1,0xaa,0x00},
{T1,0xab,0x00},{T1,0xae,0x00},{T1,0xaf,0x00},{T1,0xb0,0x0a},
{T1,0xb1,0x7a},{T1,0xb2,0x40},{T1,0xb3,0x5c},{T1,0xb4,0xf6},
{T1,0xb5,0x31},{T1,0xb6,0xc0},{T1,0xb7,0xff},{T1,0xb8,0x88},
{T1,0xb9,0xff},{T1,0xba,0xaa},{T1,0xbb,0x00},{T1,0xbc,0x08},
{T1,0xbd,0x03},{T1,0xbe,0x00},{T1,0xbf,0x00},{T1,0xc0,0xbf},
{T1,0xc1,0x00},{T1,0xc2,0x00},{T1,0xc3,0xff},{T1,0xc4,0x20},
{T1,0xc5,0x80},{T1,0xc6,0xff},{T1,0xc7,0xff},{T1,0xc8,0xff},
{T1,0xc9,0xe0},{T1,0xca,0x80},{T1,0xcb,0x00},{T1,0xcc,0x00},
{T1,0xcd,0x01},{T1,0xce,0x00},{T1,0xcf,0x54},{T1,0xd0,0x23},
{T1,0xd1,0x47},{T1,0xd2,0x01},{T1,0xd3,0x00},{T1,0xd4,0x09},
{T1,0xd5,0x47},{T1,0xd6,0x46},{T1,0xd7,0x00},{T1,0xd8,0x00},
{T1,0xd9,0xe1},{T1,0xda,0x03},{T1,0xdb,0x08},{T1,0xdc,0xb8},
{T1,0xdd,0x08},{T1,0xde,0x0c},{T1,0xdf,0x90},{T1,0xe6,0x00},
{T1,0xe7,0x00},{T1,0xe8,0x00},{T1,0xec,0x00},{T1,0xed,0x00},
{T1,0xee,0x00},{T2,0xfb,0x03},{T1,0xf0,0x00},{T1,0xf1,0x00},
{T1,0xf2,0x00},{T1,0xf3,0x00},{T1,0xf4,0x00},{T1,0xf5,0x01},
{T1,0xf7,0x00},{T1,0xf8,0x00},{T1,0xf9,0x07},{T1,0xfa,0xff},
{T1,0xfb,0x00},{T1,0xfc,0x00},{T1,0xfd,0x30},{T1,0xfe,0x00},
{T1,0xff,0x02},{C1,0x00,0xb0},{C1,0x01,0x00},{C1,0x02,0x11},
{C1,0x03,0x18},{C1,0x04,0x04},{C1,0x05,0xe0},{C1,0x06,0x5f},
{C1,0x07,0x27},{C1,0x08,0x30},{C1,0x09,0xff},{C1,0x0a,0xc0},
{C1,0x0b,0xaa},{C1,0x0c,0xbb},{C1,0x0d,0xee},{C1,0x0e,0xaa},
{C1,0x0f,0xaa},{C1,0x10,0x0d},{C1,0x11,0xab},{C1,0x12,0x0b},
{C1,0x13,0x3c},{C1,0x14,0x18},{C1,0x15,0xd9},{C1,0x16,0x51},
{C1,0x17,0xec},{C1,0x18,0x00},{C1,0x19,0xbe},{C1,0x1a,0xd6},
{C1,0x1b,0x1c},{C1,0x1c,0x0b},{C1,0x1d,0x3c},{C1,0x1e,0x29},
{C1,0x1f,0x00},{C1,0x20,0x00},{C1,0x21,0x00},{C1,0x22,0xa0},
{C1,0x23,0x94},{C1,0x24,0xaf},{C1,0x25,0x01},{C1,0x26,0x00},
{C1,0x27,0x00},{C1,0x28,0x00},{C1,0x29,0x00},{C1,0x2a,0x00},
{C1,0x2b,0x00},{C1,0x2c,0x00},{C1,0x2d,0x00},{C1,0x2e,0x00},
{C1,0x2f,0x0c},{C1,0x30,0x3b},{C1,0x31,0x41},{C1,0x32,0x0c},
{C1,0x33,0x02},{C1,0x34,0xb1},{C1,0x35,0xed},{C1,0x36,0x60},
{C1,0x37,0xcc},{C1,0x38,0x6c},{C1,0x39,0x7d},{C1,0x3a,0xb1},
{C1,0x3b,0xed},{C1,0x3c,0x69},{C1,0x3d,0xb3},{C1,0x3e,0xed},
{C1,0x3f,0x40},{C1,0x40,0xdb},{C1,0x41,0xda},{C1,0x42,0x79},
{C1,0x43,0x87},{C1,0x44,0xbc},{C1,0x45,0x3f},{C1,0x46,0xb7},
{C1,0x47,0x5e},{C1,0x48,0x1c},{C1,0x49,0xb7},{C1,0x4a,0x56},
{C1,0x4b,0xb7},{C1,0x4c,0x56},{C1,0x4d,0xb7},{C1,0x4e,0x56},
{C1,0x4f,0x63},{C1,0x50,0xd5},{C1,0x51,0x74},{C1,0x52,0x95},
{C1,0x53,0x5f},{C1,0x54,0xc0},{C1,0x55,0x73},{C1,0x56,0x28},
{C1,0x57,0xc4},{C1,0x58,0x69},{C1,0x59,0x55},{C1,0x5a,0x55},
{C1,0x5b,0x40},{C1,0x5c,0x60},{C1,0x5d,0xfd},{C1,0x5e,0x00},
{C1,0x5f,0x00},{C1,0x60,0x30},{C1,0x61,0x29},{C1,0x62,0x13},
{C1,0x63,0xf0},{C1,0x64,0x00},{C1,0x65,0x96},{C1,0x66,0x72},
{C1,0x67,0x1b},{C1,0x68,0x2d},{C1,0x69,0x97},{C1,0x6a,0x4b},
{C1,0x6b,0xde},{C1,0x6c,0x88},{C1,0x6d,0x00},{C1,0x6e,0x00},
{C1,0x6f,0x00},{C1,0x70,0xab},{C1,0x71,0x2b},{C1,0x72,0x10},
{C1,0x73,0xf4},{C1,0x74,0x47},{C1,0x75,0x57},{C1,0x76,0x40},
{C1,0x77,0xaa},{C1,0x78,0xaa},{C1,0x79,0x01},{C1,0x7a,0x00},
{C1,0x7b,0x07},{C1,0x7c,0x50},{C1,0x80,0x00},{C1,0x81,0x88},
{C1,0x82,0x00},{C1,0xf0,0x00},{C1,0xf1,0x5e},{C1,0xf2,0xec},
{C1,0xf3,0x00},{C1,0xf4,0x5e},{C1,0xf5,0xec},{C1,0xf6,0x05},
{T2,0xfb,0x03},{C1,0xfc,0x00},{C1,0xfd,0x00},{C1,0xfe,0x00},
{C1,0xff,0x02},

• Prepare DVB-T bank for firmware upload
  • Write 0x20 to register 0xf0 in T1 bank
  • Write 0x03 to register 0xf5 in T1 bank (this most likely set the mcu to reset state)
• Load firmware for demod
  • Write all firmware bytes to register 0xf6 to fill the mcu memory
• Start demod firmware
  • Write 0x00 to register 0xf5 in T1 bank
• Check parity
  • Read register 0xf8 in T1 bank, if byte 5 (0x10) is set the parity check failed.

Demod mcu

You can check if the firmware is running by reading register 0xf5.

• If bit 0 is 0 it is running
• If bit 0 is 1 it is not running

You can control the cpu by writing to the 0xf5 register:

• write 0x03 to stop the cpu
• write 0x00 to start the cpu

Demod probe

• Read register 0xFF in T2 bank

The answer should be 0x02.

TS mode

How to set chip ts mode.

Parallel TS with fixed clock

• Write 0x00 to register 0x08 in T2 bank
• Write 0xE1 to register 0xD9 in T1 bank

Parallel TS with variable clock

• Write 0x00 to register 0x08 in T2 bank
• Write 0xE3 to register 0xD9 in T1 bank

Serial TS with variable clock

• Write 0x1D to register 0x08 in T2 bank
• Write 0xE3 to register 0xD9 in T1 bank

Lock

DVB-T2

• Read register 0x92 in T2 bank.
• If the low nibble in the result is >12 there is a lock

DVB-T

• Read register 0x7F in T1 bank.
• If the low nibble in the result is >8 there is a lock

DVB-C

• Read register 0x84 in C1 bank.
• If the low nibble in the result is >7 there is a lock

When lock is detected it means what the demod has: Signal, Carrier, Viterbi, Sync and Lock.

Lock 88473

DVB-C

• Read register 0x85 in C1 bank
• If bit 6 is not set then read register 0x89 in C1 bank
• If bit 1 is set then we have lock.

DVB-T

• Read register 0x62 in T1 bank.
• If bit 5 and 7 is set then
• If the low nibble in the result is >8 there is a lock
• If the low nibble in the result is >2 there is a signal

DVB-T2

• Read register 0x8B in T2 bank.
• If bit 6 is set then
• If the low nibble in the result is >12 there is a lock

Setting Digital TV standard

Select the value representing the standard you want from the list.

DVB-T   2
DVB-T2  3
DVB-C   4

• Write the value to register 0x03 in T2 bank

Setting demod bandwidth

Select the value representing the bandwidth you want from the list.

5MHz 3
6MHz 2
7MHz 1
8MHz 0

• Write the value to register 0x04 in T2 bank

Configure demod for signal reception

• Write 0x00 to register 0xFF in T2 bank
• Write 0x66 to register 0x00 in T2 bank
• Write 0x00 to register 0x01 in T2 bank
• Write 0x02 to register 0x02 in T2 bank
• Set the Digital TV Standard
• Set the demod bandwidth

And depending on the selected standard and bandwidth configuration, write one of the following configuration to the demod:

DVB-C

{T2,0x10,0x3f},
{T2,0x11,0x50},
{T2,0x12,0x2c},
{T2,0x13,0x8f},
{T2,0x14,0x80},
{T2,0x15,0x00},
{T2,0x16,0x08},
{T2,0x17,0xee},
{T2,0x18,0x08},
{T2,0x19,0xee},
{T1,0x46,0x00},
{T1,0xae,0x00},
{T1,0xb0,0x0b},
{T1,0xb4,0x00},
{T1,0xcd,0x17},
{T1,0xd4,0x09},
{T1,0xd6,0x48},

DVB-T

Begin with a per MHz setup.

6 MHz

{T2,0x10,0x2c},
{T2,0x11,0x94},
{T2,0x12,0xdb},
{T2,0x13,0xbf},
{T2,0x14,0x55},
{T2,0x15,0x55},
{T2,0x16,0x15},
{T2,0x17,0x6b},
{T2,0x18,0x15},
{T2,0x19,0x6b},
{T1,0x46,0x00},

7 MHz

{T2,0x10,0x39},
{T2,0x11,0x11},
{T2,0x12,0xbc},
{T2,0x13,0xa4},
{T2,0x14,0x00},
{T2,0x15,0x00},
{T2,0x16,0x0f},
{T2,0x17,0x2c},
{T2,0x18,0x0f},
{T2,0x19,0x2c},
{T1,0x46,0x10},

8 MHz

{T2,0x10,0x39},
{T2,0x11,0x11},
{T2,0x12,0xbc},
{T2,0x13,0x8f},
{T2,0x14,0x80},
{T2,0x15,0x00},
{T2,0x16,0x08},
{T2,0x17,0xee},
{T2,0x18,0x08},
{T2,0x19,0xee},
{T1,0x46,0x00},

And end with a common configuration.

{T1,0xae,0x00},
{T1,0xb0,0x0a},
{T1,0xb4,0x00},
{T1,0xcd,0x1f},
{T1,0xd4,0x0a},
{T1,0xd6,0x48},

DVB-T2

Begin with a per MHz setup.

1.7 MHz

{T2,0x10,0x17},
{T2,0x11,0xba},
{T2,0x12,0x11},
{T2,0x13,0xf4},
{T2,0x14,0x6f},
{T2,0x15,0x64},
{T2,0x16,0x1c},
{T2,0x17,0x00},
{T2,0x18,0x1c},
{T2,0x19,0x00},

5 MHz

{T2,0x10,0x3e},
{T2,0x11,0x70},
{T2,0x12,0x64},
{T2,0x13,0xe5},
{T2,0x14,0x99},
{T2,0x15,0x9a},
{T2,0x16,0x1b},
{T2,0x17,0xa9},
{T2,0x18,0x1b},
{T2,0x19,0xa9},

6 MHz

{T2,0x10,0x2c},
{T2,0x11,0x94},
{T2,0x12,0xdb},
{T2,0x13,0xbf},
{T2,0x14,0x55},
{T2,0x15,0x55},
{T2,0x16,0x15},
{T2,0x17,0x6b},
{T2,0x18,0x15},
{T2,0x19,0x6b},

7 MHz

{T2,0x10,0x39},
{T2,0x11,0x11},
{T2,0x12,0xbc},
{T2,0x13,0xa4},
{T2,0x14,0x00},
{T2,0x15,0x00},
{T2,0x16,0x0f},
{T2,0x17,0x2c},
{T2,0x18,0x0f},
{T2,0x19,0x2c},

8 MHz

{T2,0x10,0x39},
{T2,0x11,0x11},
{T2,0x12,0xbc},
{T2,0x13,0x8f},
{T2,0x14,0x80},
{T2,0x15,0x00},
{T2,0x16,0x08},
{T2,0x17,0xee},
{T2,0x18,0x08},
{T2,0x19,0xee},

And end with a common configuration.

{T1,0x46,0x00},
{T1,0xae,0x00},
{T1,0xb0,0x0a},
{T1,0xb4,0xf6},
{T1,0xcd,0x01},
{T1,0xd4,0x09},
{T1,0xd6,0x46},

{T2,0x30,0x80},
{T2,0x32,0x00},
{T2,0xf8,0x9f},

Statistics

Signal strength

• Read register 0x8E (upper agc reg) in T2 bank
• Read register 0x8F (lower agc reg) in T2 bank
• Return both values ored together

Firmware version

• Read register 0xF1 in T bank
• The returned value is the firmware version

PER

• Read register 0xE1 in T bank (upper)
• Read register 0xE2 in T bank (lower)
• Or both values as error
• Read register 0xE3 in T bank (upper)
• Read register 0xE4 in T bank (lower)
• Or both values as per_len
• Return error * 100 / per_len

MN88473 uses 0xDD to 0xE0

CNR (Carrier Noise Ratio)

DVB-T

MN88473 uses 0x8F and 0x90

• Read register 0x9C in T bank (upper)
• Read register 0x9D in T bank (lower)
• Or both values as value
• if value is 0 then cnr is 0
• calculate 10log of 65536 divided by value and then add 200 as result
• if result is less then 0 cnr is 0
• take result divided by 100 as cnr

DVB-T2

MN88473 uses 0xB8 and 0xB9 and 0xB7 for flag

• Read register 0xBD in T2 bank (upper)
• Read register 0xBE in T2 bank (lower)
• Or both registers as value
• If value is 0 cnr is 0
• Read register 0xBC in T2 bank as flag
• If bit 2 in flag is set (MISO)
  • calculate 10log of 16384 divided by value and then subtract 600 as result
  • if result is less then 0 cnr is 0
• If bit 2 in flag is not set (SISO)
  • calculate 10log of 65536 divided by value and then add 200 as result
  • if result is less then 0 cnr is 0
• take result divided by 100 as cnr

DVB-C

MN88473 uses the same registers.

• Read register 0xA1 in C bank (upper)
• Read register 0xA2 in C bank (lower)
• Or both registers as carrier
• Read register 0xA3 in C bank (upper)
• Read register 0xA4 in C bank (lower)
• Or both registers as noise
• if noise is 0 cnr is 0
• calculate 10log of signal multiplied by 8 and divided by noise as result
• if result is less then 0 cnr is 0
• take result divided by 100 as cnr

BER (Bit Error Rate)

DVB-T/C

• Read register 0x78 in T bank as value
• And value with 0xDF
• Write register 0x78 in T bank from value
• Read register 0x7D in T bank as value
• And value with 0xF0 and then or with 0x5
• Write register 0x7D in T bank from value
• Read register 0x9F in T bank (upper)
• Read register 0xA0 in T bank (middle)
• Read register 0xA1 in T bank (lower)
• Or together as error
• Read register 0xA2 in T bank (upper)
• Read register 0xA3 in T bank (lower)
• Or together as value
• Take value and multiply with 8 and 203 as sum
• Take sum divided by error as ber

DVB-T2

• Read register 0x8A in T2 bank as value
• Or value with 0x20 then and with 0xef as value
• Write register 0x8A in T2 bank from value
• Read register 0xC0 in T2 bank (upper)
• Read register 0xC1 in T2 bank (middle)
• Read register 0xC2 in T2 bank (lower)
• Or together as error
• Read register 0x8B in T2 bank as berlen
• Write register 0xC5 in T2 bank with 0x3
• If berlen bit 0 is set (fec_type)
  • Bit 2 to 4 in berlen forms an index into the following table, take value as fec_type_m
  • 32400, 38880, 43200, 48600, 51840, 54000
  • Take berlen low nibble shifted up 1 time multiplied with fec_type_m as sum
• If berlen bit 0 is not set (fec_type)
  • Bit 2 to 4 in berlen forms an index into the following table, take value as fec_type_m
  • 28800, 38880, 43200, 47520, 50400, 53280
  • Take berlen low nibble shifted up 1 time multiplied with fec_type_m as sum
• Take sum divided by error as ber

DVB-T Signal Properties

TPS length indicator

• Read register 0x88 in T bank
• Bit 0 to 6 forms a length value

Hierarchy

• Read register 0x89 in T bank
• Bit 0 to 2 forms an index to the following table

0, No heirarchy
1, alpha=1
2, alpha=2
3, alpha=4
4, Unknown (not defined)
5, Unknown (not defined)
6, Unknown (not defined)
7, Unknown (not defined)

Constellation

• Read register 0x89 in T bank
• Bit 3 and 4 forms an index to the following table

0, QPSK
1, 16QAM
2, 64QAM
3, Unknown (not defined)

FFT Mode

• Read register 0x8B in T bank
• Bit 0 and 1 forms an index to the following table

0, 2k
1, 8k
2, 4k
3, Unknown (not defined)

Guard Interval

• Read register 0x8B in T bank
• Bit 2 and 3 forms an index to the following table

0, 1/32
1, 1/16
2, 1/8
3, 1/4

FEC High Priority Code Rate

• Read register 0x8A in T bank
• Bit 3 and 5 forms an index to the following table

0, 1/2
1, 2/3
2, 3/4
3, 5/6
4, 7/8
5, Unknown (not defined)

FEC Low Priority Code Rate

• Read register 0x8A in T bank
• Bit 0 to 2 forms an index to the following table

0, 1/2
1, 2/3
2, 3/4
3, 5/6
4, 7/8
5, Unknown (not defined)

Cell ID

• Read register 0x90 (upper) in T bank
• Read register 0x91 (lower) in T bank
• Return both values ored together

DVB-T Signal Properties MN88473

TPS length indicator

• Read register 0x6C in T bank
• Bit 0 to 5 forms a length value

Hierarchy

• Read register 0x6D in T bank
• Bit 0 to 2 forms an index to the following table

0, No heirarchy
1, alpha=1
2, alpha=2
3, alpha=4
4, Unknown (not defined)
5, Unknown (not defined)
6, Unknown (not defined)
7, Unknown (not defined)

Constellation

• Read register 0x6D in T bank
• Bit 3 and 4 forms an index to the following table

0, QPSK
1, 16QAM
2, 64QAM
3, Unknown (not defined)

FFT Mode

• Read register 0x6F in T bank
• Bit 0 and 1 forms an index to the following table

0, 2k
1, 8k
2, 4k
3, Unknown (not defined)

Guard Interval

• Read register 0x6F in T bank
• Bit 2 and 3 forms an index to the following table

0, 1/32
1, 1/16
2, 1/8
3, 1/4

FEC High Priority Code Rate

• Read register 0x6e in T bank
• Bit 4 to 6 forms an index to the following table

0, 1/2
1, 2/3
2, 3/4
3, 5/6
4, 7/8
5, Unknown (not defined)

FEC Low Priority Code Rate

• Read register 0x8A in T bank
• Bit 0 to 3 forms an index to the following table

0, 1/2
1, 2/3
2, 3/4
3, 5/6
4, 7/8
5, Unknown (not defined)

Cell ID

• Read register 0x74 (upper) in T bank
• Read register 0x75 (lower) in T bank
• Return both values ored together

DVB-T2 Signal Properties

MN88473 uses 0x93 and 0x94 as I/O registers.

Error Free

• Read register 0xC3 in T2 bank as value
• Invert only bit 0 in value and return the result of the inversion

Guard Interval

• Write 0x0 to register 0xC4 in T2 bank
• Write 0x0 to register 0xC5 in T2 bank
• Read register 0xC8 in T2 bank
• Bit 4 to 6 forms an index to the following table

0, 1/32
1, 1/16
2, 1/8
3, 1/4
4, 1/128
5, 19/128
6, 19/256
7, Unknown (not defined)

Selected PLP

• Read register 0x32 in T2 bank
• Return result

Type

• Write 0x0 to register 0xC4 in T2 bank
• Write 0x0 to register 0xC5 in T2 bank
• Read register 0xC6 in T2 bank
• Bit 0 to 7 forms an index to the following table

0, TS
1, GS
2, TS and GS
*, Unknown (not defined)

Bandwidth Ext

• Write 0x0 to register 0xC4 in T2 bank
• Write 0x0 to register 0xC5 in T2 bank
• Read register 0xC7 in T2 bank
• Return the value of bit 7

FFT Mode

• Read register 0x93 in T2 bank
• Bit 0 to 2 forms an index to the following table

0, 1k
1, 2k
2, 4k
3, 8k
4, 16k
5, 32k

S1

• Write 0x0 to register 0xC4 in T2 bank
• Write 0x0 to register 0xC5 in T2 bank
• Read register 0xC7 in T2 bank
• Bit 4 to 6 forms a value s1

S2

• Write 0x0 to register 0xC4 in T2 bank
• Write 0x0 to register 0xC5 in T2 bank
• Read register 0xC7 in T2 bank
• Bit 0 to 3 forms a value s2

PAPR

• Write 0x0 to register 0xC4 in T2 bank
• Write 0x0 to register 0xC5 in T2 bank
• Read register 0xC8 in T2 bank
• Bit 0 to 4 forms an index to the following table

0, No PAPR
1, ACE-PAPR
2, TR-PAPR
3, ACE and PAPR
*, Unknown (not defined)

L1 Modulation

• Write 0x0 to register 0xC4 in T2 bank
• Write 0x0 to register 0xC5 in T2 bank
• Read register 0xC9 in T2 bank
• Bit 4 to 7 forms an index to the following table

0, BPSK
1, QPSK
2, 16QAM
3, 64QAM
*, Unknown (not defined)

L1 Code Rate

• Write 0x0 to register 0xC4 in T2 bank
• Write 0x0 to register 0xC5 in T2 bank
• Read register 0xC9 in T2 bank
• Bit 2 and 3 forms an index to the following table

0, 1/2
1, 3/5
2, 2/3
3, 3/4

L1 Fec Type

• Write 0x0 to register 0xC4 in T2 bank
• Write 0x0 to register 0xC5 in T2 bank
• Read register 0xC9 in T2 bank
• Bit 0 and 1 forms a value as fec_type

DVB-C Signal Properties

Modulation

(Same for MN88473)

• Read register 0x83 in C bank
• Bit 0 to 2 forms an index to the following table

0, QAM64
1, QAM256
2, QAM128
3, QAM32
4, QAM16
5, Reserved
6, Reserved
7, Reserved