FPGA fw for NetUP Dual Universal CI

NetUP Dual Universal CI (NetUP_Dual_Universal_CI) built on FPGA: EP4CGX22CF19C8

Series: Cyclone IV GX
Number of Logic Elements/Cells: 21280
Total RAM Bits: 774144
Number of 3.125-Gbps transceivers: 4
Package: 324-FBGA (19x19)

Obtain firmware source code

Source code of firmware distributed under GPLv3 license and available on github:

git clone https://github.com/aospan/NetUP_Dual_Universal_CI-fpga

Firmware compilation

• Install Altera Quartus II Web Edition (free). Current version 14.1
• Open project (File->Open Project) Dual_Universal_CI.qpf
• Run "Processing -> Start Compilation". Compilation will take about 6 minutes on fast CPU
• Resulting firmware placed into out/netup_unidvb_top.sof file

Firmware preparation to upload into NetUP Universal Dual DVB-CI card

netup_unidvb_top.sof file should be converted to netup_unidvb_top.bin. Below commands tested on Ubuntu Linux 14.10 with Altera Quartus II installed into /mnt/sdb/altera/14.1 and openjdk-8-jre package installed

• setup environment

$ /mnt/sdb/altera/14.1/nios2eds/nios2_command_shell.sh
------------------------------------------------
Altera Nios2 Command Shell [GCC 4]

Version 14.1, Build 186
------------------------------------------------

• conversion to srec

$ java -Xmx512m -jar /mnt/sdb/altera/14.1/nios2eds/bin/sof2flash.jar --input=netup_unidvb_top.sof --output=netup_unidvb_top.srec --compress --epcs --offset=0
Info: *******************************************************************
Info: Running Quartus II 64-Bit Convert_programming_file
Info: Command: quartus_cpf --no_banner --convert --device=EPCS128 --option=netup_unidvb_top.opt netup_unidvb_top.sof netup_unidvb_top.pof
Info (210033): Memory Map File netup_unidvb_top.map contains memory usage information for file netup_unidvb_top.pof
Info: Quartus II 64-Bit Convert_programming_file was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 441 megabytes
    Info: Processing ended: Fri Feb 13 13:24:09 2015
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:02
Info: *******************************************************************
Info: Running Quartus II 64-Bit Convert_programming_file
Info: Command: quartus_cpf --no_banner --convert netup_unidvb_top.pof netup_unidvb_top.rpd
Info: Quartus II 64-Bit Convert_programming_file was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 434 megabytes
    Info: Processing ended: Fri Feb 13 13:24:13 2015
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:02

• conversion to bin

$ /mnt/sdb/altera/14.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/nios2-elf-objcopy -I srec -O binary netup_unidvb_top.srec netup_unidvb_top.bin

Upload firmware (netup_unidvb_top.bin) to NetUP Universal Dual DVB-CI card

• load m25p80 (if not already loaded)

$ modprobe m25p80

• reload netup_unidvb.ko with spi_enable=1

$ rmmod netup_unidvb && modprobe netup_unidvb spi_enable=1

• check mtd file for proper mtd device number

$ cat /proc/mtd
dev:    size   erasesize  name
mtd0: 01000000 00040000 "fpga_04:00.0"

• write firmware to flash

$ flashcp -v netup_unidvb_top.bin /dev/mtd0
Erasing blocks: 2/2 (100%)
Writing data: 387k/0k (100%)
Verifying data: 387k/0k (100%)

DONE

Remember to POWER OFF card (reset not enough) to new firmware take effect !

FPGA resource usage

For firmware based on source code from 13 Feb 2015:

Total logic elements	12,892 / 21,280 ( 61 % )
Total combinational functions	11,717 / 21,280 ( 55 % )
Dedicated logic registers	7,126 / 21,280 ( 33 % )
Total registers	7265
Total pins	147 / 167 ( 88 % )
Total virtual pins	0
Total memory bits	447,200 / 774,144 ( 58 % )
Embedded Multiplier 9-bit elements	0 / 80 ( 0 % )
Total GXB Receiver Channel PCS	1 / 4 ( 25 % )
Total GXB Receiver Channel PMA	1 / 4 ( 25 % )
Total GXB Transmitter Channel PCS	1 / 4 ( 25 % )
Total GXB Transmitter Channel PMA	1 / 4 ( 25 % )
Total PLLs	3 / 4 ( 75 % )

• 

  FPGA physical layout

FPGA Simulation

Simulation files available in folder testbench. Some parts of firmware can be simulated (without real hardware).

• start modelsim

$ /mnt/sdb/altera/14.1/modelsim_ase/bin/vsim

• Open (File->Open) dvb_unici.mpf

• In "Library" remove "work" and create it again (workaround for problem in modelsim)

• Run "Compile->Compile All"

• Choose Project (for example, "ci_control_tb") and run "Execute"

• Do simulation with "Simulate -> Run"

• 

  Simulation waveform screen