/*
 * Intel ACPI Component Architecture
 * AML/ASL+ Disassembler version 20160831-64
 * Copyright (c) 2000 - 2016 Intel Corporation
 * 
 * Disassembling to symbolic ASL+ operators
 *
 * Disassembly of ssdt10.dat, Sun Sep  4 22:12:50 2016
 *
 * Original Table Header:
 *     Signature        "SSDT"
 *     Length           0x0000015F (351)
 *     Revision         0x01
 *     Checksum         0x09
 *     OEM ID           "PmRef"
 *     OEM Table ID     "ApIst"
 *     OEM Revision     0x00003000 (12288)
 *     Compiler ID      "INTL"
 *     Compiler Version 0x20120913 (538052883)
 */
DefinitionBlock ("", "SSDT", 1, "PmRef", "ApIst", 0x00003000)
{
    External (_PR_.CPU0._PCT, IntObj)
    External (_PR_.CPU0._PPC, IntObj)
    External (_PR_.CPU0._PSD, IntObj)
    External (_PR_.CPU0._PSS, IntObj)
    External (_PR_.CPU1, DeviceObj)
    External (_PR_.CPU2, DeviceObj)
    External (_PR_.CPU3, DeviceObj)

    Scope (\_PR.CPU1)
    {
        Method (_PPC, 0, NotSerialized)  // _PPC: Performance Present Capabilities
        {
            Return (\_PR.CPU0._PPC) /* External reference */
        }

        Method (_PCT, 0, NotSerialized)  // _PCT: Performance Control
        {
            Return (\_PR.CPU0._PCT) /* External reference */
        }

        Method (_PSS, 0, NotSerialized)  // _PSS: Performance Supported States
        {
            Return (\_PR.CPU0._PSS) /* External reference */
        }

        Method (_PSD, 0, NotSerialized)  // _PSD: Power State Dependencies
        {
            Return (\_PR.CPU0._PSD) /* External reference */
        }
    }

    Scope (\_PR.CPU2)
    {
        Method (_PPC, 0, NotSerialized)  // _PPC: Performance Present Capabilities
        {
            Return (\_PR.CPU0._PPC) /* External reference */
        }

        Method (_PCT, 0, NotSerialized)  // _PCT: Performance Control
        {
            Return (\_PR.CPU0._PCT) /* External reference */
        }

        Method (_PSS, 0, NotSerialized)  // _PSS: Performance Supported States
        {
            Return (\_PR.CPU0._PSS) /* External reference */
        }

        Method (_PSD, 0, NotSerialized)  // _PSD: Power State Dependencies
        {
            Return (\_PR.CPU0._PSD) /* External reference */
        }
    }

    Scope (\_PR.CPU3)
    {
        Method (_PPC, 0, NotSerialized)  // _PPC: Performance Present Capabilities
        {
            Return (\_PR.CPU0._PPC) /* External reference */
        }

        Method (_PCT, 0, NotSerialized)  // _PCT: Performance Control
        {
            Return (\_PR.CPU0._PCT) /* External reference */
        }

        Method (_PSS, 0, NotSerialized)  // _PSS: Performance Supported States
        {
            Return (\_PR.CPU0._PSS) /* External reference */
        }

        Method (_PSD, 0, NotSerialized)  // _PSD: Power State Dependencies
        {
            Return (\_PR.CPU0._PSD) /* External reference */
        }
    }
}


/*
Raw Table Data: Length 351 (0x15F)

  0000: 53 53 44 54 5F 01 00 00 01 09 50 6D 52 65 66 00  // SSDT_.....PmRef.
  0010: 41 70 49 73 74 00 00 00 00 30 00 00 49 4E 54 4C  // ApIst....0..INTL
  0020: 13 09 12 20 10 48 06 5C 2E 5F 50 52 5F 43 50 55  // ... .H.\._PR_CPU
  0030: 31 14 16 5F 50 50 43 00 A4 5C 2F 03 5F 50 52 5F  // 1.._PPC..\/._PR_
  0040: 43 50 55 30 5F 50 50 43 14 16 5F 50 43 54 00 A4  // CPU0_PPC.._PCT..
  0050: 5C 2F 03 5F 50 52 5F 43 50 55 30 5F 50 43 54 14  // \/._PR_CPU0_PCT.
  0060: 16 5F 50 53 53 00 A4 5C 2F 03 5F 50 52 5F 43 50  // ._PSS..\/._PR_CP
  0070: 55 30 5F 50 53 53 14 16 5F 50 53 44 00 A4 5C 2F  // U0_PSS.._PSD..\/
  0080: 03 5F 50 52 5F 43 50 55 30 5F 50 53 44 10 48 06  // ._PR_CPU0_PSD.H.
  0090: 5C 2E 5F 50 52 5F 43 50 55 32 14 16 5F 50 50 43  // \._PR_CPU2.._PPC
  00A0: 00 A4 5C 2F 03 5F 50 52 5F 43 50 55 30 5F 50 50  // ..\/._PR_CPU0_PP
  00B0: 43 14 16 5F 50 43 54 00 A4 5C 2F 03 5F 50 52 5F  // C.._PCT..\/._PR_
  00C0: 43 50 55 30 5F 50 43 54 14 16 5F 50 53 53 00 A4  // CPU0_PCT.._PSS..
  00D0: 5C 2F 03 5F 50 52 5F 43 50 55 30 5F 50 53 53 14  // \/._PR_CPU0_PSS.
  00E0: 16 5F 50 53 44 00 A4 5C 2F 03 5F 50 52 5F 43 50  // ._PSD..\/._PR_CP
  00F0: 55 30 5F 50 53 44 10 48 06 5C 2E 5F 50 52 5F 43  // U0_PSD.H.\._PR_C
  0100: 50 55 33 14 16 5F 50 50 43 00 A4 5C 2F 03 5F 50  // PU3.._PPC..\/._P
  0110: 52 5F 43 50 55 30 5F 50 50 43 14 16 5F 50 43 54  // R_CPU0_PPC.._PCT
  0120: 00 A4 5C 2F 03 5F 50 52 5F 43 50 55 30 5F 50 43  // ..\/._PR_CPU0_PC
  0130: 54 14 16 5F 50 53 53 00 A4 5C 2F 03 5F 50 52 5F  // T.._PSS..\/._PR_
  0140: 43 50 55 30 5F 50 53 53 14 16 5F 50 53 44 00 A4  // CPU0_PSS.._PSD..
  0150: 5C 2F 03 5F 50 52 5F 43 50 55 30 5F 50 53 44     // \/._PR_CPU0_PSD
 */