/* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20160831-64 * Copyright (c) 2000 - 2016 Intel Corporation * * Disassembling to symbolic ASL+ operators * * Disassembly of ssdt4.dat, Sun Sep 4 22:12:50 2016 * * Original Table Header: * Signature "SSDT" * Length 0x00000763 (1891) * Revision 0x01 * Checksum 0x9B * OEM ID "PmRef" * OEM Table ID "CpuPm" * OEM Revision 0x00003000 (12288) * Compiler ID "INTL" * Compiler Version 0x20120913 (538052883) */ DefinitionBlock ("", "SSDT", 1, "PmRef", "CpuPm", 0x00003000) { External (_PR_.CPU0, DeviceObj) External (_PR_.CPU1, DeviceObj) External (_PR_.CPU2, DeviceObj) External (_PR_.CPU3, DeviceObj) Scope (\) { Name (SSDT, Package (0x0C) { "CPU0IST ", 0x79DC6618, 0x0000057B, "APIST ", 0x79DC7E18, 0x0000015F, "CPU0CST ", 0x79DC6C18, 0x000003A5, "APCST ", 0x79DC8E18, 0x0000008D }) Name (CFGD, 0x73B92803) Name (\PDC0, 0x80000000) Name (\PDC1, 0x80000000) Name (\PDC2, 0x80000000) Name (\PDC3, 0x80000000) Name (\SDTL, Zero) } Scope (\_PR.CPU0) { Name (HI0, Zero) Name (HC0, Zero) Method (_PDC, 1, NotSerialized) // _PDC: Processor Driver Capabilities { Local0 = CPDC (Arg0) GCAP (Local0) } Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities { Local0 = COSC (Arg0, Arg1, Arg2, Arg3) GCAP (Local0) Return (Local0) } Method (CPDC, 1, NotSerialized) { CreateDWordField (Arg0, Zero, REVS) CreateDWordField (Arg0, 0x04, SIZE) Local0 = SizeOf (Arg0) Local1 = (Local0 - 0x08) CreateField (Arg0, 0x40, (Local1 * 0x08), TEMP) Name (STS0, Buffer (0x04) { 0x00, 0x00, 0x00, 0x00 /* .... */ }) Concatenate (STS0, TEMP, Local2) Return (COSC (ToUUID ("4077a616-290c-47be-9ebd-d87058713953"), REVS, SIZE, Local2)) } Method (COSC, 4, NotSerialized) { CreateDWordField (Arg3, Zero, STS0) CreateDWordField (Arg3, 0x04, CAP0) CreateDWordField (Arg0, Zero, IID0) CreateDWordField (Arg0, 0x04, IID1) CreateDWordField (Arg0, 0x08, IID2) CreateDWordField (Arg0, 0x0C, IID3) Name (UID0, ToUUID ("4077a616-290c-47be-9ebd-d87058713953")) CreateDWordField (UID0, Zero, EID0) CreateDWordField (UID0, 0x04, EID1) CreateDWordField (UID0, 0x08, EID2) CreateDWordField (UID0, 0x0C, EID3) If (!(((IID0 == EID0) && (IID1 == EID1)) && (( IID2 == EID2) && (IID3 == EID3)))) { STS0 = 0x06 Return (Arg3) } If (Arg1 != One) { STS0 = 0x0A Return (Arg3) } Return (Arg3) } Method (GCAP, 1, NotSerialized) { CreateDWordField (Arg0, Zero, STS0) CreateDWordField (Arg0, 0x04, CAP0) If ((STS0 == 0x06) || (STS0 == 0x0A)) { Return (Zero) } If (STS0 & One) { CAP0 &= 0x0BFF Return (Zero) } PDC0 = ((PDC0 & 0x7FFFFFFF) | CAP0) /* \_PR_.CPU0.GCAP.CAP0 */ If (CFGD & One) { If (((CFGD & 0x01000000) && ((PDC0 & 0x09) == 0x09)) && !(SDTL & One)) { SDTL |= One OperationRegion (IST0, SystemMemory, DerefOf (SSDT [One]), DerefOf (SSDT [0x02])) Load (IST0, HI0) /* \_PR_.CPU0.HI0_ */ } } If (CFGD & 0x82) { If (((CFGD & 0x01000000) && (PDC0 & 0x18)) && ! (SDTL & 0x02)) { SDTL |= 0x02 OperationRegion (CST0, SystemMemory, DerefOf (SSDT [0x07]), DerefOf (SSDT [0x08])) Load (CST0, HC0) /* \_PR_.CPU0.HC0_ */ } } Return (Zero) } } Scope (\_PR.CPU1) { Name (HI1, Zero) Name (HC1, Zero) Method (_PDC, 1, NotSerialized) // _PDC: Processor Driver Capabilities { Local0 = \_PR.CPU0.CPDC (Arg0) GCAP (Local0) } Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities { Local0 = \_PR.CPU0.COSC (Arg0, Arg1, Arg2, Arg3) GCAP (Local0) Return (Local0) } Method (GCAP, 1, NotSerialized) { CreateDWordField (Arg0, Zero, STS1) CreateDWordField (Arg0, 0x04, CAP1) If ((STS1 == 0x06) || (STS1 == 0x0A)) { Return (Zero) } If (STS1 & One) { CAP1 &= 0x0BFF Return (Zero) } PDC1 = ((PDC1 & 0x7FFFFFFF) | CAP1) /* \_PR_.CPU1.GCAP.CAP1 */ If ((PDC0 & 0x09) == 0x09) { APPT () } If (PDC0 & 0x18) { APCT () } Return (Zero) } Method (APCT, 0, NotSerialized) { If ((CFGD & 0x82) && !(SDTL & 0x20)) { SDTL |= 0x20 OperationRegion (CST1, SystemMemory, DerefOf (SSDT [0x0A]), DerefOf (SSDT [0x0B])) Load (CST1, HC1) /* \_PR_.CPU1.HC1_ */ } } Method (APPT, 0, NotSerialized) { If ((CFGD & One) && !(SDTL & 0x10)) { SDTL |= 0x10 OperationRegion (IST1, SystemMemory, DerefOf (SSDT [0x04]), DerefOf (SSDT [0x05])) Load (IST1, HI1) /* \_PR_.CPU1.HI1_ */ } } } Scope (\_PR.CPU2) { Name (HI1, Zero) Name (HC1, Zero) Method (_PDC, 1, NotSerialized) // _PDC: Processor Driver Capabilities { Local0 = \_PR.CPU0.CPDC (Arg0) GCAP (Local0) } Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities { Local0 = \_PR.CPU0.COSC (Arg0, Arg1, Arg2, Arg3) GCAP (Local0) Return (Local0) } Method (GCAP, 1, NotSerialized) { CreateDWordField (Arg0, Zero, STS1) CreateDWordField (Arg0, 0x04, CAP1) If ((STS1 == 0x06) || (STS1 == 0x0A)) { Return (Zero) } If (STS1 & One) { CAP1 &= 0x0BFF Return (Zero) } PDC1 = ((PDC1 & 0x7FFFFFFF) | CAP1) /* \_PR_.CPU2.GCAP.CAP1 */ If ((PDC0 & 0x09) == 0x09) { APPT () } If (PDC0 & 0x18) { APCT () } Return (Zero) } Method (APCT, 0, NotSerialized) { If ((CFGD & 0x82) && !(SDTL & 0x20)) { SDTL |= 0x20 OperationRegion (CST1, SystemMemory, DerefOf (SSDT [0x0A]), DerefOf (SSDT [0x0B])) Load (CST1, HC1) /* \_PR_.CPU2.HC1_ */ } } Method (APPT, 0, NotSerialized) { If ((CFGD & One) && !(SDTL & 0x10)) { SDTL |= 0x10 OperationRegion (IST1, SystemMemory, DerefOf (SSDT [0x04]), DerefOf (SSDT [0x05])) Load (IST1, HI1) /* \_PR_.CPU2.HI1_ */ } } } Scope (\_PR.CPU3) { Name (HI1, Zero) Name (HC1, Zero) Method (_PDC, 1, NotSerialized) // _PDC: Processor Driver Capabilities { Local0 = \_PR.CPU0.CPDC (Arg0) GCAP (Local0) } Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities { Local0 = \_PR.CPU0.COSC (Arg0, Arg1, Arg2, Arg3) GCAP (Local0) Return (Local0) } Method (GCAP, 1, NotSerialized) { CreateDWordField (Arg0, Zero, STS1) CreateDWordField (Arg0, 0x04, CAP1) If ((STS1 == 0x06) || (STS1 == 0x0A)) { Return (Zero) } If (STS1 & One) { CAP1 &= 0x0BFF Return (Zero) } PDC1 = ((PDC1 & 0x7FFFFFFF) | CAP1) /* \_PR_.CPU3.GCAP.CAP1 */ If ((PDC0 & 0x09) == 0x09) { APPT () } If (PDC0 & 0x18) { APCT () } Return (Zero) } Method (APCT, 0, NotSerialized) { If ((CFGD & 0x82) && !(SDTL & 0x20)) { SDTL |= 0x20 OperationRegion (CST1, SystemMemory, DerefOf (SSDT [0x0A]), DerefOf (SSDT [0x0B])) Load (CST1, HC1) /* \_PR_.CPU3.HC1_ */ } } Method (APPT, 0, NotSerialized) { If ((CFGD & One) && !(SDTL & 0x10)) { SDTL |= 0x10 OperationRegion (IST1, SystemMemory, DerefOf (SSDT [0x04]), DerefOf (SSDT [0x05])) Load (IST1, HI1) /* \_PR_.CPU3.HI1_ */ } } } } /* Raw Table Data: Length 1891 (0x763) 0000: 53 53 44 54 63 07 00 00 01 9B 50 6D 52 65 66 00 // SSDTc.....PmRef. 0010: 43 70 75 50 6D 00 00 00 00 30 00 00 49 4E 54 4C // CpuPm....0..INTL 0020: 13 09 12 20 10 4A 09 5C 00 08 53 53 44 54 12 43 // ... .J.\..SSDT.C 0030: 05 0C 0D 43 50 55 30 49 53 54 20 00 0C 18 66 DC // ...CPU0IST ...f. 0040: 79 0C 7B 05 00 00 0D 41 50 49 53 54 20 20 20 00 // y.{....APIST . 0050: 0C 18 7E DC 79 0C 5F 01 00 00 0D 43 50 55 30 43 // ..~.y._....CPU0C 0060: 53 54 20 00 0C 18 6C DC 79 0C A5 03 00 00 0D 41 // ST ...l.y......A 0070: 50 43 53 54 20 20 20 00 0C 18 8E DC 79 0C 8D 00 // PCST .....y... 0080: 00 00 08 43 46 47 44 0C 03 28 B9 73 08 5C 50 44 // ...CFGD..(.s.\PD 0090: 43 30 0C 00 00 00 80 08 5C 50 44 43 31 0C 00 00 // C0......\PDC1... 00A0: 00 80 08 5C 50 44 43 32 0C 00 00 00 80 08 5C 50 // ...\PDC2......\P 00B0: 44 43 33 0C 00 00 00 80 08 5C 53 44 54 4C 00 10 // DC3......\SDTL.. 00C0: 44 27 5C 2E 5F 50 52 5F 43 50 55 30 08 48 49 30 // D'\._PR_CPU0.HI0 00D0: 5F 00 08 48 43 30 5F 00 14 12 5F 50 44 43 01 70 // _..HC0_..._PDC.p 00E0: 43 50 44 43 68 60 47 43 41 50 60 14 17 5F 4F 53 // CPDCh`GCAP`.._OS 00F0: 43 04 70 43 4F 53 43 68 69 6A 6B 60 47 43 41 50 // C.pCOSChijk`GCAP 0100: 60 A4 60 14 48 06 43 50 44 43 01 8A 68 00 52 45 // `.`.H.CPDC..h.RE 0110: 56 53 8A 68 0A 04 53 49 5A 45 70 87 68 60 70 74 // VS.h..SIZEp.h`pt 0120: 60 0A 08 00 61 5B 13 68 0A 40 77 61 0A 08 00 54 // `...a[.h.@wa...T 0130: 45 4D 50 08 53 54 53 30 11 07 0A 04 00 00 00 00 // EMP.STS0........ 0140: 73 53 54 53 30 54 45 4D 50 62 A4 43 4F 53 43 11 // sSTS0TEMPb.COSC. 0150: 13 0A 10 16 A6 77 40 0C 29 BE 47 9E BD D8 70 58 // .....w@.).G...pX 0160: 71 39 53 52 45 56 53 53 49 5A 45 62 14 4D 0B 43 // q9SREVSSIZEb.M.C 0170: 4F 53 43 04 8A 6B 00 53 54 53 30 8A 6B 0A 04 43 // OSC..k.STS0.k..C 0180: 41 50 30 8A 68 00 49 49 44 30 8A 68 0A 04 49 49 // AP0.h.IID0.h..II 0190: 44 31 8A 68 0A 08 49 49 44 32 8A 68 0A 0C 49 49 // D1.h..IID2.h..II 01A0: 44 33 08 55 49 44 30 11 13 0A 10 16 A6 77 40 0C // D3.UID0......w@. 01B0: 29 BE 47 9E BD D8 70 58 71 39 53 8A 55 49 44 30 // ).G...pXq9S.UID0 01C0: 00 45 49 44 30 8A 55 49 44 30 0A 04 45 49 44 31 // .EID0.UID0..EID1 01D0: 8A 55 49 44 30 0A 08 45 49 44 32 8A 55 49 44 30 // .UID0..EID2.UID0 01E0: 0A 0C 45 49 44 33 A0 32 92 90 90 93 49 49 44 30 // ..EID3.2....IID0 01F0: 45 49 44 30 93 49 49 44 31 45 49 44 31 90 93 49 // EID0.IID1EID1..I 0200: 49 44 32 45 49 44 32 93 49 49 44 33 45 49 44 33 // ID2EID2.IID3EID3 0210: 70 0A 06 53 54 53 30 A4 6B A0 0E 92 93 69 01 70 // p..STS0.k....i.p 0220: 0A 0A 53 54 53 30 A4 6B A4 6B 14 49 10 47 43 41 // ..STS0.k.k.I.GCA 0230: 50 01 8A 68 00 53 54 53 30 8A 68 0A 04 43 41 50 // P..h.STS0.h..CAP 0240: 30 A0 12 91 93 53 54 53 30 0A 06 93 53 54 53 30 // 0....STS0...STS0 0250: 0A 0A A4 00 A0 16 7B 53 54 53 30 01 00 7B 43 41 // ......{STS0..{CA 0260: 50 30 0B FF 0B 43 41 50 30 A4 00 7D 7B 50 44 43 // P0...CAP0..}{PDC 0270: 30 0C FF FF FF 7F 00 43 41 50 30 50 44 43 30 A0 // 0......CAP0PDC0. 0280: 48 05 7B 43 46 47 44 01 00 A0 4E 04 90 90 7B 43 // H.{CFGD...N...{C 0290: 46 47 44 0C 00 00 00 01 00 93 7B 50 44 43 30 0A // FGD.......{PDC0. 02A0: 09 00 0A 09 92 7B 53 44 54 4C 01 00 7D 53 44 54 // .....{SDTL..}SDT 02B0: 4C 01 53 44 54 4C 5B 80 49 53 54 30 00 83 88 53 // L.SDTL[.IST0...S 02C0: 53 44 54 01 00 83 88 53 53 44 54 0A 02 00 5B 20 // SDT....SSDT...[ 02D0: 49 53 54 30 48 49 30 5F A0 49 05 7B 43 46 47 44 // IST0HI0_.I.{CFGD 02E0: 0A 82 00 A0 4E 04 90 90 7B 43 46 47 44 0C 00 00 // ....N...{CFGD... 02F0: 00 01 00 7B 50 44 43 30 0A 18 00 92 7B 53 44 54 // ...{PDC0....{SDT 0300: 4C 0A 02 00 7D 53 44 54 4C 0A 02 53 44 54 4C 5B // L...}SDTL..SDTL[ 0310: 80 43 53 54 30 00 83 88 53 53 44 54 0A 07 00 83 // .CST0...SSDT.... 0320: 88 53 53 44 54 0A 08 00 5B 20 43 53 54 30 48 43 // .SSDT...[ CST0HC 0330: 30 5F A4 00 10 44 16 5C 2E 5F 50 52 5F 43 50 55 // 0_...D.\._PR_CPU 0340: 31 08 48 49 31 5F 00 08 48 43 31 5F 00 14 1D 5F // 1.HI1_..HC1_..._ 0350: 50 44 43 01 70 5C 2F 03 5F 50 52 5F 43 50 55 30 // PDC.p\/._PR_CPU0 0360: 43 50 44 43 68 60 47 43 41 50 60 14 22 5F 4F 53 // CPDCh`GCAP`."_OS 0370: 43 04 70 5C 2F 03 5F 50 52 5F 43 50 55 30 43 4F // C.p\/._PR_CPU0CO 0380: 53 43 68 69 6A 6B 60 47 43 41 50 60 A4 60 14 45 // SChijk`GCAP`.`.E 0390: 07 47 43 41 50 01 8A 68 00 53 54 53 31 8A 68 0A // .GCAP..h.STS1.h. 03A0: 04 43 41 50 31 A0 12 91 93 53 54 53 31 0A 06 93 // .CAP1....STS1... 03B0: 53 54 53 31 0A 0A A4 00 A0 16 7B 53 54 53 31 01 // STS1......{STS1. 03C0: 00 7B 43 41 50 31 0B FF 0B 43 41 50 31 A4 00 7D // .{CAP1...CAP1..} 03D0: 7B 50 44 43 31 0C FF FF FF 7F 00 43 41 50 31 50 // {PDC1......CAP1P 03E0: 44 43 31 A0 10 93 7B 50 44 43 30 0A 09 00 0A 09 // DC1...{PDC0..... 03F0: 41 50 50 54 A0 0D 7B 50 44 43 30 0A 18 00 41 50 // APPT..{PDC0...AP 0400: 43 54 A4 00 14 4A 04 41 50 43 54 00 A0 42 04 90 // CT...J.APCT..B.. 0410: 7B 43 46 47 44 0A 82 00 92 7B 53 44 54 4C 0A 20 // {CFGD....{SDTL. 0420: 00 7D 53 44 54 4C 0A 20 53 44 54 4C 5B 80 43 53 // .}SDTL. SDTL[.CS 0430: 54 31 00 83 88 53 53 44 54 0A 0A 00 83 88 53 53 // T1...SSDT.....SS 0440: 44 54 0A 0B 00 5B 20 43 53 54 31 48 43 31 5F 14 // DT...[ CST1HC1_. 0450: 49 04 41 50 50 54 00 A0 41 04 90 7B 43 46 47 44 // I.APPT..A..{CFGD 0460: 01 00 92 7B 53 44 54 4C 0A 10 00 7D 53 44 54 4C // ...{SDTL...}SDTL 0470: 0A 10 53 44 54 4C 5B 80 49 53 54 31 00 83 88 53 // ..SDTL[.IST1...S 0480: 53 44 54 0A 04 00 83 88 53 53 44 54 0A 05 00 5B // SDT.....SSDT...[ 0490: 20 49 53 54 31 48 49 31 5F 10 44 16 5C 2E 5F 50 // IST1HI1_.D.\._P 04A0: 52 5F 43 50 55 32 08 48 49 31 5F 00 08 48 43 31 // R_CPU2.HI1_..HC1 04B0: 5F 00 14 1D 5F 50 44 43 01 70 5C 2F 03 5F 50 52 // _..._PDC.p\/._PR 04C0: 5F 43 50 55 30 43 50 44 43 68 60 47 43 41 50 60 // _CPU0CPDCh`GCAP` 04D0: 14 22 5F 4F 53 43 04 70 5C 2F 03 5F 50 52 5F 43 // ."_OSC.p\/._PR_C 04E0: 50 55 30 43 4F 53 43 68 69 6A 6B 60 47 43 41 50 // PU0COSChijk`GCAP 04F0: 60 A4 60 14 45 07 47 43 41 50 01 8A 68 00 53 54 // `.`.E.GCAP..h.ST 0500: 53 31 8A 68 0A 04 43 41 50 31 A0 12 91 93 53 54 // S1.h..CAP1....ST 0510: 53 31 0A 06 93 53 54 53 31 0A 0A A4 00 A0 16 7B // S1...STS1......{ 0520: 53 54 53 31 01 00 7B 43 41 50 31 0B FF 0B 43 41 // STS1..{CAP1...CA 0530: 50 31 A4 00 7D 7B 50 44 43 31 0C FF FF FF 7F 00 // P1..}{PDC1...... 0540: 43 41 50 31 50 44 43 31 A0 10 93 7B 50 44 43 30 // CAP1PDC1...{PDC0 0550: 0A 09 00 0A 09 41 50 50 54 A0 0D 7B 50 44 43 30 // .....APPT..{PDC0 0560: 0A 18 00 41 50 43 54 A4 00 14 4A 04 41 50 43 54 // ...APCT...J.APCT 0570: 00 A0 42 04 90 7B 43 46 47 44 0A 82 00 92 7B 53 // ..B..{CFGD....{S 0580: 44 54 4C 0A 20 00 7D 53 44 54 4C 0A 20 53 44 54 // DTL. .}SDTL. SDT 0590: 4C 5B 80 43 53 54 31 00 83 88 53 53 44 54 0A 0A // L[.CST1...SSDT.. 05A0: 00 83 88 53 53 44 54 0A 0B 00 5B 20 43 53 54 31 // ...SSDT...[ CST1 05B0: 48 43 31 5F 14 49 04 41 50 50 54 00 A0 41 04 90 // HC1_.I.APPT..A.. 05C0: 7B 43 46 47 44 01 00 92 7B 53 44 54 4C 0A 10 00 // {CFGD...{SDTL... 05D0: 7D 53 44 54 4C 0A 10 53 44 54 4C 5B 80 49 53 54 // }SDTL..SDTL[.IST 05E0: 31 00 83 88 53 53 44 54 0A 04 00 83 88 53 53 44 // 1...SSDT.....SSD 05F0: 54 0A 05 00 5B 20 49 53 54 31 48 49 31 5F 10 44 // T...[ IST1HI1_.D 0600: 16 5C 2E 5F 50 52 5F 43 50 55 33 08 48 49 31 5F // .\._PR_CPU3.HI1_ 0610: 00 08 48 43 31 5F 00 14 1D 5F 50 44 43 01 70 5C // ..HC1_..._PDC.p\ 0620: 2F 03 5F 50 52 5F 43 50 55 30 43 50 44 43 68 60 // /._PR_CPU0CPDCh` 0630: 47 43 41 50 60 14 22 5F 4F 53 43 04 70 5C 2F 03 // GCAP`."_OSC.p\/. 0640: 5F 50 52 5F 43 50 55 30 43 4F 53 43 68 69 6A 6B // _PR_CPU0COSChijk 0650: 60 47 43 41 50 60 A4 60 14 45 07 47 43 41 50 01 // `GCAP`.`.E.GCAP. 0660: 8A 68 00 53 54 53 31 8A 68 0A 04 43 41 50 31 A0 // .h.STS1.h..CAP1. 0670: 12 91 93 53 54 53 31 0A 06 93 53 54 53 31 0A 0A // ...STS1...STS1.. 0680: A4 00 A0 16 7B 53 54 53 31 01 00 7B 43 41 50 31 // ....{STS1..{CAP1 0690: 0B FF 0B 43 41 50 31 A4 00 7D 7B 50 44 43 31 0C // ...CAP1..}{PDC1. 06A0: FF FF FF 7F 00 43 41 50 31 50 44 43 31 A0 10 93 // .....CAP1PDC1... 06B0: 7B 50 44 43 30 0A 09 00 0A 09 41 50 50 54 A0 0D // {PDC0.....APPT.. 06C0: 7B 50 44 43 30 0A 18 00 41 50 43 54 A4 00 14 4A // {PDC0...APCT...J 06D0: 04 41 50 43 54 00 A0 42 04 90 7B 43 46 47 44 0A // .APCT..B..{CFGD. 06E0: 82 00 92 7B 53 44 54 4C 0A 20 00 7D 53 44 54 4C // ...{SDTL. .}SDTL 06F0: 0A 20 53 44 54 4C 5B 80 43 53 54 31 00 83 88 53 // . SDTL[.CST1...S 0700: 53 44 54 0A 0A 00 83 88 53 53 44 54 0A 0B 00 5B // SDT.....SSDT...[ 0710: 20 43 53 54 31 48 43 31 5F 14 49 04 41 50 50 54 // CST1HC1_.I.APPT 0720: 00 A0 41 04 90 7B 43 46 47 44 01 00 92 7B 53 44 // ..A..{CFGD...{SD 0730: 54 4C 0A 10 00 7D 53 44 54 4C 0A 10 53 44 54 4C // TL...}SDTL..SDTL 0740: 5B 80 49 53 54 31 00 83 88 53 53 44 54 0A 04 00 // [.IST1...SSDT... 0750: 83 88 53 53 44 54 0A 05 00 5B 20 49 53 54 31 48 // ..SSDT...[ IST1H 0760: 49 31 5F // I1_ */