/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20160831-64
* Copyright (c) 2000 - 2016 Intel Corporation
*
* Disassembling to symbolic ASL+ operators
*
* Disassembly of ssdt5.dat, Sun Sep 4 22:12:50 2016
*
* Original Table Header:
* Signature "SSDT"
* Length 0x00000290 (656)
* Revision 0x01
* Checksum 0x08
* OEM ID "PmRef"
* OEM Table ID "Cpu0Tst"
* OEM Revision 0x00003000 (12288)
* Compiler ID "INTL"
* Compiler Version 0x20120913 (538052883)
*/
DefinitionBlock ("", "SSDT", 1, "PmRef", "Cpu0Tst", 0x00003000)
{
External (_PR_.CPU0, DeviceObj)
External (_PSS, IntObj)
External (CFGD, UnknownObj)
External (PDC0, UnknownObj)
Scope (\_PR.CPU0)
{
Name (_TPC, Zero) // _TPC: Throttling Present Capabilities
Method (_PTC, 0, NotSerialized) // _PTC: Processor Throttling Control
{
If (PDC0 & 0x04)
{
Return (Package (0x02)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
}
})
}
Return (Package (0x02)
{
ResourceTemplate ()
{
Register (SystemIO,
0x04, // Bit Width
0x01, // Bit Offset
0x0000000000000410, // Address
,)
},
ResourceTemplate ()
{
Register (SystemIO,
0x04, // Bit Width
0x01, // Bit Offset
0x0000000000000410, // Address
,)
}
})
}
Name (TSSI, Package (0x08)
{
Package (0x05)
{
0x64,
0x03E8,
Zero,
Zero,
Zero
},
Package (0x05)
{
0x58,
0x036B,
Zero,
0x0F,
Zero
},
Package (0x05)
{
0x4B,
0x02EE,
Zero,
0x0E,
Zero
},
Package (0x05)
{
0x3F,
0x0271,
Zero,
0x0D,
Zero
},
Package (0x05)
{
0x32,
0x01F4,
Zero,
0x0C,
Zero
},
Package (0x05)
{
0x26,
0x0177,
Zero,
0x0B,
Zero
},
Package (0x05)
{
0x19,
0xFA,
Zero,
0x0A,
Zero
},
Package (0x05)
{
0x0D,
0x7D,
Zero,
0x09,
Zero
}
})
Name (TSSM, Package (0x08)
{
Package (0x05)
{
0x64,
0x03E8,
Zero,
Zero,
Zero
},
Package (0x05)
{
0x58,
0x036B,
Zero,
0x1E,
Zero
},
Package (0x05)
{
0x4B,
0x02EE,
Zero,
0x1C,
Zero
},
Package (0x05)
{
0x3F,
0x0271,
Zero,
0x1A,
Zero
},
Package (0x05)
{
0x32,
0x01F4,
Zero,
0x18,
Zero
},
Package (0x05)
{
0x26,
0x0177,
Zero,
0x16,
Zero
},
Package (0x05)
{
0x19,
0xFA,
Zero,
0x14,
Zero
},
Package (0x05)
{
0x0D,
0x7D,
Zero,
0x12,
Zero
}
})
Name (TSSF, Zero)
Method (_TSS, 0, NotSerialized) // _TSS: Throttling Supported States
{
If (!TSSF && CondRefOf (_PSS))
{
Local0 = _PSS /* External reference */
Local1 = SizeOf (Local0)
Local1--
Local2 = DerefOf (DerefOf (Local0 [Local1]) [One])
Local3 = Zero
While (Local3 < SizeOf (TSSI))
{
Local4 = ((Local2 * (0x08 - Local3)) / 0x08)
DerefOf (TSSI [Local3]) [One] = Local4
DerefOf (TSSM [Local3]) [One] = Local4
Local3++
}
TSSF = Ones
}
If (PDC0 & 0x04)
{
Return (TSSM) /* \_PR_.CPU0.TSSM */
}
Return (TSSI) /* \_PR_.CPU0.TSSI */
}
Method (_TDL, 0, NotSerialized) // _TDL: T-State Depth Limit
{
Debug = "Cpu0: _TDL Called"
Name (LFMI, Zero)
LFMI = SizeOf (TSSM)
LFMI--
Return (LFMI) /* \_PR_.CPU0._TDL.LFMI */
}
Method (_TSD, 0, NotSerialized) // _TSD: Throttling State Dependencies
{
If ((CFGD & 0x00800000) && !(PDC0 & 0x04))
{
Return (Package (0x01)
{
Package (0x05)
{
0x05,
Zero,
Zero,
0xFD,
0x04
}
})
}
If ((CFGD & 0x01000000) && !(PDC0 & 0x04))
{
Return (Package (0x01)
{
Package (0x05)
{
0x05,
Zero,
Zero,
0xFD,
0x02
}
})
}
Return (Package (0x01)
{
Package (0x05)
{
0x05,
Zero,
Zero,
0xFC,
One
}
})
}
}
}
/*
Raw Table Data: Length 656 (0x290)
0000: 53 53 44 54 90 02 00 00 01 08 50 6D 52 65 66 00 // SSDT......PmRef.
0010: 43 70 75 30 54 73 74 00 00 30 00 00 49 4E 54 4C // Cpu0Tst..0..INTL
0020: 13 09 12 20 10 4B 26 5C 2E 5F 50 52 5F 43 50 55 // ... .K&\._PR_CPU
0030: 30 08 5F 54 50 43 00 14 4D 06 5F 50 54 43 00 A0 // 0._TPC..M._PTC..
0040: 37 7B 50 44 43 30 0A 04 00 A4 12 2C 02 11 14 0A // 7{PDC0.....,....
0050: 11 82 0C 00 7F 00 00 00 00 00 00 00 00 00 00 00 // ................
0060: 79 00 11 14 0A 11 82 0C 00 7F 00 00 00 00 00 00 // y...............
0070: 00 00 00 00 00 79 00 A4 12 2C 02 11 14 0A 11 82 // .....y...,......
0080: 0C 00 01 04 01 00 10 04 00 00 00 00 00 00 79 00 // ..............y.
0090: 11 14 0A 11 82 0C 00 01 04 01 00 10 04 00 00 00 // ................
00A0: 00 00 00 79 00 08 54 53 53 49 12 40 06 08 12 0A // ...y..TSSI.@....
00B0: 05 0A 64 0B E8 03 00 00 00 12 0B 05 0A 58 0B 6B // ..d..........X.k
00C0: 03 00 0A 0F 00 12 0B 05 0A 4B 0B EE 02 00 0A 0E // .........K......
00D0: 00 12 0B 05 0A 3F 0B 71 02 00 0A 0D 00 12 0B 05 // .....?.q........
00E0: 0A 32 0B F4 01 00 0A 0C 00 12 0B 05 0A 26 0B 77 // .2...........&.w
00F0: 01 00 0A 0B 00 12 0A 05 0A 19 0A FA 00 0A 0A 00 // ................
0100: 12 0A 05 0A 0D 0A 7D 00 0A 09 00 08 54 53 53 4D // ......}.....TSSM
0110: 12 40 06 08 12 0A 05 0A 64 0B E8 03 00 00 00 12 // .@......d.......
0120: 0B 05 0A 58 0B 6B 03 00 0A 1E 00 12 0B 05 0A 4B // ...X.k.........K
0130: 0B EE 02 00 0A 1C 00 12 0B 05 0A 3F 0B 71 02 00 // ...........?.q..
0140: 0A 1A 00 12 0B 05 0A 32 0B F4 01 00 0A 18 00 12 // .......2........
0150: 0B 05 0A 26 0B 77 01 00 0A 16 00 12 0A 05 0A 19 // ...&.w..........
0160: 0A FA 00 0A 14 00 12 0A 05 0A 0D 0A 7D 00 0A 12 // ............}...
0170: 00 08 54 53 53 46 00 14 4F 07 5F 54 53 53 00 A0 // ..TSSF..O._TSS..
0180: 43 06 90 92 54 53 53 46 5B 12 5F 50 53 53 00 70 // C...TSSF[._PSS.p
0190: 5F 50 53 53 60 70 87 60 61 76 61 70 83 88 83 88 // _PSS`p.`avap....
01A0: 60 61 00 01 00 62 70 00 63 A2 33 95 63 87 54 53 // `a...bp.c.3.c.TS
01B0: 53 49 70 78 77 62 74 0A 08 63 00 00 0A 08 00 00 // SIpxwbt..c......
01C0: 64 70 64 88 83 88 54 53 53 49 63 00 01 00 70 64 // dpd...TSSIc...pd
01D0: 88 83 88 54 53 53 4D 63 00 01 00 75 63 70 FF 54 // ...TSSMc...ucp.T
01E0: 53 53 46 A0 0E 7B 50 44 43 30 0A 04 00 A4 54 53 // SSF..{PDC0....TS
01F0: 53 4D A4 54 53 53 49 14 36 5F 54 44 4C 00 70 0D // SM.TSSI.6_TDL.p.
0200: 43 70 75 30 3A 20 5F 54 44 4C 20 43 61 6C 6C 65 // Cpu0: _TDL Calle
0210: 64 00 5B 31 08 4C 46 4D 49 00 70 87 54 53 53 4D // d.[1.LFMI.p.TSSM
0220: 4C 46 4D 49 76 4C 46 4D 49 A4 4C 46 4D 49 14 41 // LFMIvLFMI.LFMI.A
0230: 06 5F 54 53 44 00 A0 25 90 7B 43 46 47 44 0C 00 // ._TSD..%.{CFGD..
0240: 00 80 00 00 92 7B 50 44 43 30 0A 04 00 A4 12 0D // .....{PDC0......
0250: 01 12 0A 05 0A 05 00 00 0A FD 0A 04 A0 25 90 7B // .............%.{
0260: 43 46 47 44 0C 00 00 00 01 00 92 7B 50 44 43 30 // CFGD.......{PDC0
0270: 0A 04 00 A4 12 0D 01 12 0A 05 0A 05 00 00 0A FD // ................
0280: 0A 02 A4 12 0C 01 12 09 05 0A 05 00 00 0A FC 01 // ................
*/