/*
 * Intel ACPI Component Architecture
 * AML/ASL+ Disassembler version 20160831-64
 * Copyright (c) 2000 - 2016 Intel Corporation
 * 
 * Disassembling to symbolic ASL+ operators
 *
 * Disassembly of ssdt6.dat, Sun Sep  4 22:12:50 2016
 *
 * Original Table Header:
 *     Signature        "SSDT"
 *     Length           0x0000017A (378)
 *     Revision         0x01
 *     Checksum         0x5F
 *     OEM ID           "PmRef"
 *     OEM Table ID     "ApTst"
 *     OEM Revision     0x00003000 (12288)
 *     Compiler ID      "INTL"
 *     Compiler Version 0x20120913 (538052883)
 */
DefinitionBlock ("", "SSDT", 1, "PmRef", "ApTst", 0x00003000)
{
    External (_PR_.CPU0._PTC, IntObj)
    External (_PR_.CPU0._TSS, IntObj)
    External (_PR_.CPU1, DeviceObj)
    External (_PR_.CPU2, DeviceObj)
    External (_PR_.CPU3, DeviceObj)
    External (MPEN, UnknownObj)
    External (PDC0, UnknownObj)

    Scope (\_PR.CPU1)
    {
        Name (_TPC, Zero)  // _TPC: Throttling Present Capabilities
        Method (_PTC, 0, NotSerialized)  // _PTC: Processor Throttling Control
        {
            Return (\_PR.CPU0._PTC) /* External reference */
        }

        Method (_TSS, 0, NotSerialized)  // _TSS: Throttling Supported States
        {
            Return (\_PR.CPU0._TSS) /* External reference */
        }

        Method (_TSD, 0, NotSerialized)  // _TSD: Throttling State Dependencies
        {
            If (!(PDC0 & 0x04))
            {
                Return (Package (0x01)
                {
                    Package (0x05)
                    {
                        0x05, 
                        Zero, 
                        Zero, 
                        0xFD, 
                        MPEN
                    }
                })
            }

            Return (Package (0x01)
            {
                Package (0x05)
                {
                    0x05, 
                    Zero, 
                    One, 
                    0xFC, 
                    One
                }
            })
        }
    }

    Scope (\_PR.CPU2)
    {
        Name (_TPC, Zero)  // _TPC: Throttling Present Capabilities
        Method (_PTC, 0, NotSerialized)  // _PTC: Processor Throttling Control
        {
            Return (\_PR.CPU0._PTC) /* External reference */
        }

        Method (_TSS, 0, NotSerialized)  // _TSS: Throttling Supported States
        {
            Return (\_PR.CPU0._TSS) /* External reference */
        }

        Method (_TSD, 0, NotSerialized)  // _TSD: Throttling State Dependencies
        {
            If (!(PDC0 & 0x04))
            {
                Return (Package (0x01)
                {
                    Package (0x05)
                    {
                        0x05, 
                        Zero, 
                        Zero, 
                        0xFD, 
                        MPEN
                    }
                })
            }

            Return (Package (0x01)
            {
                Package (0x05)
                {
                    0x05, 
                    Zero, 
                    One, 
                    0xFC, 
                    One
                }
            })
        }
    }

    Scope (\_PR.CPU3)
    {
        Name (_TPC, Zero)  // _TPC: Throttling Present Capabilities
        Method (_PTC, 0, NotSerialized)  // _PTC: Processor Throttling Control
        {
            Return (\_PR.CPU0._PTC) /* External reference */
        }

        Method (_TSS, 0, NotSerialized)  // _TSS: Throttling Supported States
        {
            Return (\_PR.CPU0._TSS) /* External reference */
        }

        Method (_TSD, 0, NotSerialized)  // _TSD: Throttling State Dependencies
        {
            If (!(PDC0 & 0x04))
            {
                Return (Package (0x01)
                {
                    Package (0x05)
                    {
                        0x05, 
                        Zero, 
                        Zero, 
                        0xFD, 
                        MPEN
                    }
                })
            }

            Return (Package (0x01)
            {
                Package (0x05)
                {
                    0x05, 
                    Zero, 
                    One, 
                    0xFC, 
                    One
                }
            })
        }
    }
}


/*
Raw Table Data: Length 378 (0x17A)

  0000: 53 53 44 54 7A 01 00 00 01 5F 50 6D 52 65 66 00  // SSDTz...._PmRef.
  0010: 41 70 54 73 74 00 00 00 00 30 00 00 49 4E 54 4C  // ApTst....0..INTL
  0020: 13 09 12 20 10 41 07 5C 2E 5F 50 52 5F 43 50 55  // ... .A.\._PR_CPU
  0030: 31 08 5F 54 50 43 00 14 16 5F 50 54 43 00 A4 5C  // 1._TPC..._PTC..\
  0040: 2F 03 5F 50 52 5F 43 50 55 30 5F 50 54 43 14 16  // /._PR_CPU0_PTC..
  0050: 5F 54 53 53 00 A4 5C 2F 03 5F 50 52 5F 43 50 55  // _TSS..\/._PR_CPU
  0060: 30 5F 54 53 53 14 30 5F 54 53 44 00 A0 1B 92 7B  // 0_TSS.0_TSD....{
  0070: 50 44 43 30 0A 04 00 A4 12 0F 01 12 0C 05 0A 05  // PDC0............
  0080: 00 00 0A FD 4D 50 45 4E A4 12 0C 01 12 09 05 0A  // ....MPEN........
  0090: 05 00 01 0A FC 01 10 41 07 5C 2E 5F 50 52 5F 43  // .......A.\._PR_C
  00A0: 50 55 32 08 5F 54 50 43 00 14 16 5F 50 54 43 00  // PU2._TPC..._PTC.
  00B0: A4 5C 2F 03 5F 50 52 5F 43 50 55 30 5F 50 54 43  // .\/._PR_CPU0_PTC
  00C0: 14 16 5F 54 53 53 00 A4 5C 2F 03 5F 50 52 5F 43  // .._TSS..\/._PR_C
  00D0: 50 55 30 5F 54 53 53 14 30 5F 54 53 44 00 A0 1B  // PU0_TSS.0_TSD...
  00E0: 92 7B 50 44 43 30 0A 04 00 A4 12 0F 01 12 0C 05  // .{PDC0..........
  00F0: 0A 05 00 00 0A FD 4D 50 45 4E A4 12 0C 01 12 09  // ......MPEN......
  0100: 05 0A 05 00 01 0A FC 01 10 41 07 5C 2E 5F 50 52  // .........A.\._PR
  0110: 5F 43 50 55 33 08 5F 54 50 43 00 14 16 5F 50 54  // _CPU3._TPC..._PT
  0120: 43 00 A4 5C 2F 03 5F 50 52 5F 43 50 55 30 5F 50  // C..\/._PR_CPU0_P
  0130: 54 43 14 16 5F 54 53 53 00 A4 5C 2F 03 5F 50 52  // TC.._TSS..\/._PR
  0140: 5F 43 50 55 30 5F 54 53 53 14 30 5F 54 53 44 00  // _CPU0_TSS.0_TSD.
  0150: A0 1B 92 7B 50 44 43 30 0A 04 00 A4 12 0F 01 12  // ...{PDC0........
  0160: 0C 05 0A 05 00 00 0A FD 4D 50 45 4E A4 12 0C 01  // ........MPEN....
  0170: 12 09 05 0A 05 00 01 0A FC 01                    // ..........
 */