/* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20160831-64 * Copyright (c) 2000 - 2016 Intel Corporation * * Disassembling to symbolic ASL+ operators * * Disassembly of ssdt9.dat, Sun Sep 4 22:12:50 2016 * * Original Table Header: * Signature "SSDT" * Length 0x000003A5 (933) * Revision 0x01 * Checksum 0xFC * OEM ID "PmRef" * OEM Table ID "Cpu0Cst" * OEM Revision 0x00003001 (12289) * Compiler ID "INTL" * Compiler Version 0x20120913 (538052883) */ DefinitionBlock ("", "SSDT", 1, "PmRef", "Cpu0Cst", 0x00003001) { External (_PR_.CPU0, DeviceObj) External (CFGD, UnknownObj) External (PDC0, UnknownObj) Scope (\_PR.CPU0) { OperationRegion (DEB0, SystemIO, 0x80, One) Field (DEB0, ByteAcc, NoLock, Preserve) { DBG8, 8 } Method (_CST, 0, NotSerialized) // _CST: C-States { DBG8 = 0x60 If ((CFGD & 0x01000000) && !(PDC0 & 0x10)) { DBG8 = 0x61 Return (Package (0x02) { One, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) }, One, 0x9D, 0x03E8 } }) } If ((CFGD & 0x00200000) && (PDC0 & 0x0200)) { If (CFGD & 0x2000) { DBG8 = 0x77 Return (Package (0x04) { 0x03, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000000, // Address 0x01, // Access Size ) }, One, One, 0x03E8 }, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000058, // Address 0x01, // Access Size ) }, 0x02, 0x01F4, 0x0A }, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000064, // Address 0x01, // Access Size ) }, 0x03, 0x03E8, 0x0A } }) } If (CFGD & 0x0800) { DBG8 = 0x76 Return (Package (0x03) { 0x02, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000000, // Address 0x01, // Access Size ) }, One, One, 0x03E8 }, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000058, // Address 0x01, // Access Size ) }, 0x02, 0x01F4, 0x0A } }) } DBG8 = 0x71 Return (Package (0x02) { One, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000000, // Address 0x01, // Access Size ) }, One, One, 0x03E8 } }) } If ((CFGD & 0x00200000) && (PDC0 & 0x0100)) { If (CFGD & 0x2000) { DBG8 = 0x87 Return (Package (0x04) { 0x03, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000000, // Address 0x01, // Access Size ) }, One, One, 0x03E8 }, Package (0x04) { ResourceTemplate () { Register (SystemIO, 0x08, // Bit Width 0x00, // Bit Offset 0x0000000000000416, // Address ,) }, 0x02, 0x01F4, 0x64 }, Package (0x04) { ResourceTemplate () { Register (SystemIO, 0x08, // Bit Width 0x00, // Bit Offset 0x0000000000000417, // Address ,) }, 0x03, 0x03E8, 0x0A } }) } If (CFGD & 0x0800) { DBG8 = 0x86 Return (Package (0x03) { 0x02, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000000, // Address 0x01, // Access Size ) }, One, One, 0x03E8 }, Package (0x04) { ResourceTemplate () { Register (SystemIO, 0x08, // Bit Width 0x00, // Bit Offset 0x0000000000000416, // Address ,) }, 0x02, 0x01F4, 0x0A } }) } DBG8 = 0x81 Return (Package (0x02) { One, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000000, // Address 0x01, // Access Size ) }, One, One, 0x03E8 } }) } If (CFGD & 0x2000) { DBG8 = 0x97 Return (Package (0x04) { 0x03, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) }, One, One, 0x03E8 }, Package (0x04) { ResourceTemplate () { Register (SystemIO, 0x08, // Bit Width 0x00, // Bit Offset 0x0000000000000416, // Address ,) }, 0x02, 0x01F4, 0x64 }, Package (0x04) { ResourceTemplate () { Register (SystemIO, 0x08, // Bit Width 0x00, // Bit Offset 0x0000000000000417, // Address ,) }, 0x03, 0x1388, 0x0A } }) } If (CFGD & 0x0800) { DBG8 = 0x96 Return (Package (0x03) { 0x02, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) }, One, One, 0x03E8 }, Package (0x04) { ResourceTemplate () { Register (SystemIO, 0x08, // Bit Width 0x00, // Bit Offset 0x0000000000000416, // Address ,) }, 0x02, 0x01F4, 0x0A } }) } DBG8 = 0x91 Return (Package (0x02) { One, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) }, One, One, 0x03E8 } }) } } } /* Raw Table Data: Length 933 (0x3A5) 0000: 53 53 44 54 A5 03 00 00 01 FC 50 6D 52 65 66 00 // SSDT......PmRef. 0010: 43 70 75 30 43 73 74 00 01 30 00 00 49 4E 54 4C // Cpu0Cst..0..INTL 0020: 13 09 12 20 10 40 38 5C 2E 5F 50 52 5F 43 50 55 // ... .@8\._PR_CPU 0030: 30 5B 80 44 45 42 30 01 0A 80 01 5B 81 0B 44 45 // 0[.DEB0....[..DE 0040: 42 30 01 44 42 47 38 08 14 4C 35 5F 43 53 54 00 // B0.DBG8..L5_CST. 0050: 70 0A 60 44 42 47 38 A0 41 04 90 7B 43 46 47 44 // p.`DBG8.A..{CFGD 0060: 0C 00 00 00 01 00 92 7B 50 44 43 30 0A 10 00 70 // .......{PDC0...p 0070: 0A 61 44 42 47 38 A4 12 21 02 01 12 1D 04 11 14 // .aDBG8..!....... 0080: 0A 11 82 0C 00 7F 00 00 00 00 00 00 00 00 00 00 // ................ 0090: 00 79 00 01 0A 9D 0B E8 03 A0 4B 10 90 7B 43 46 // .y........K..{CF 00A0: 47 44 0C 00 00 20 00 00 7B 50 44 43 30 0B 00 02 // GD... ..{PDC0... 00B0: 00 A0 44 07 7B 43 46 47 44 0B 00 20 00 70 0A 77 // ..D.{CFGD.. .p.w 00C0: 44 42 47 38 A4 12 40 06 04 0A 03 12 1C 04 11 14 // DBG8..@......... 00D0: 0A 11 82 0C 00 7F 01 02 01 00 00 00 00 00 00 00 // ................ 00E0: 00 79 00 01 01 0B E8 03 12 1E 04 11 14 0A 11 82 // .y.............. 00F0: 0C 00 7F 01 02 01 58 00 00 00 00 00 00 00 79 00 // ......X.......y. 0100: 0A 02 0B F4 01 0A 0A 12 1E 04 11 14 0A 11 82 0C // ................ 0110: 00 7F 01 02 01 64 00 00 00 00 00 00 00 79 00 0A // .....d.......y.. 0120: 03 0B E8 03 0A 0A A0 45 05 7B 43 46 47 44 0B 00 // .......E.{CFGD.. 0130: 08 00 70 0A 76 44 42 47 38 A4 12 41 04 03 0A 02 // ..p.vDBG8..A.... 0140: 12 1C 04 11 14 0A 11 82 0C 00 7F 01 02 01 00 00 // ................ 0150: 00 00 00 00 00 00 79 00 01 01 0B E8 03 12 1E 04 // ......y......... 0160: 11 14 0A 11 82 0C 00 7F 01 02 01 58 00 00 00 00 // ...........X.... 0170: 00 00 00 79 00 0A 02 0B F4 01 0A 0A 70 0A 71 44 // ...y........p.qD 0180: 42 47 38 A4 12 20 02 01 12 1C 04 11 14 0A 11 82 // BG8.. .......... 0190: 0C 00 7F 01 02 01 00 00 00 00 00 00 00 00 79 00 // ..............y. 01A0: 01 01 0B E8 03 A0 4B 10 90 7B 43 46 47 44 0C 00 // ......K..{CFGD.. 01B0: 00 20 00 00 7B 50 44 43 30 0B 00 01 00 A0 44 07 // . ..{PDC0.....D. 01C0: 7B 43 46 47 44 0B 00 20 00 70 0A 87 44 42 47 38 // {CFGD.. .p..DBG8 01D0: A4 12 40 06 04 0A 03 12 1C 04 11 14 0A 11 82 0C // ..@............. 01E0: 00 7F 01 02 01 00 00 00 00 00 00 00 00 79 00 01 // .............y.. 01F0: 01 0B E8 03 12 1E 04 11 14 0A 11 82 0C 00 01 08 // ................ 0200: 00 00 16 04 00 00 00 00 00 00 79 00 0A 02 0B F4 // ..........y..... 0210: 01 0A 64 12 1E 04 11 14 0A 11 82 0C 00 01 08 00 // ..d............. 0220: 00 17 04 00 00 00 00 00 00 79 00 0A 03 0B E8 03 // .........y...... 0230: 0A 0A A0 45 05 7B 43 46 47 44 0B 00 08 00 70 0A // ...E.{CFGD....p. 0240: 86 44 42 47 38 A4 12 41 04 03 0A 02 12 1C 04 11 // .DBG8..A........ 0250: 14 0A 11 82 0C 00 7F 01 02 01 00 00 00 00 00 00 // ................ 0260: 00 00 79 00 01 01 0B E8 03 12 1E 04 11 14 0A 11 // ..y............. 0270: 82 0C 00 01 08 00 00 16 04 00 00 00 00 00 00 79 // ...............y 0280: 00 0A 02 0B F4 01 0A 0A 70 0A 81 44 42 47 38 A4 // ........p..DBG8. 0290: 12 20 02 01 12 1C 04 11 14 0A 11 82 0C 00 7F 01 // . .............. 02A0: 02 01 00 00 00 00 00 00 00 00 79 00 01 01 0B E8 // ..........y..... 02B0: 03 A0 44 07 7B 43 46 47 44 0B 00 20 00 70 0A 97 // ..D.{CFGD.. .p.. 02C0: 44 42 47 38 A4 12 40 06 04 0A 03 12 1C 04 11 14 // DBG8..@......... 02D0: 0A 11 82 0C 00 7F 00 00 00 00 00 00 00 00 00 00 // ................ 02E0: 00 79 00 01 01 0B E8 03 12 1E 04 11 14 0A 11 82 // .y.............. 02F0: 0C 00 01 08 00 00 16 04 00 00 00 00 00 00 79 00 // ..............y. 0300: 0A 02 0B F4 01 0A 64 12 1E 04 11 14 0A 11 82 0C // ......d......... 0310: 00 01 08 00 00 17 04 00 00 00 00 00 00 79 00 0A // .............y.. 0320: 03 0B 88 13 0A 0A A0 45 05 7B 43 46 47 44 0B 00 // .......E.{CFGD.. 0330: 08 00 70 0A 96 44 42 47 38 A4 12 41 04 03 0A 02 // ..p..DBG8..A.... 0340: 12 1C 04 11 14 0A 11 82 0C 00 7F 00 00 00 00 00 // ................ 0350: 00 00 00 00 00 00 79 00 01 01 0B E8 03 12 1E 04 // ......y......... 0360: 11 14 0A 11 82 0C 00 01 08 00 00 16 04 00 00 00 // ................ 0370: 00 00 00 79 00 0A 02 0B F4 01 0A 0A 70 0A 91 44 // ...y........p..D 0380: 42 47 38 A4 12 20 02 01 12 1C 04 11 14 0A 11 82 // BG8.. .......... 0390: 0C 00 7F 00 00 00 00 00 00 00 00 00 00 00 79 00 // ..............y. 03A0: 01 01 0B E8 03 // ..... */